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    Electronic device
    11.
    发明授权
    Electronic device 有权

    公开(公告)号：US11831306B2

    公开(公告)日：2023-11-28

    申请号：US17836181

    申请日：2022-06-09

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  David Zipperstein ,  Juergen Schaefer ,  Holger Dienst ,  Markus Bichl ,  Ralph Mueller-Eschenbach ,  Arndt Voigtlaender

    IPC: H03K17/56 ,  H03M3/00 ,  G01S7/03

    CPC classification number: H03K17/56 ,  H03M3/458 ,  H03M3/50 ,  G01S7/03

    Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

    Determining a state of a memory cell
    13.
    发明授权
    Determining a state of a memory cell 有权

    公开(公告)号：US10236041B2

    公开(公告)日：2019-03-19

    申请号：US15597846

    申请日：2017-05-17

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Thomas Kern ,  Christian Peters

    IPC: G11C7/22 ,  G11C7/06 ,  G11C13/00 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32

    Abstract: A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

    Sense amplifier of a memory cell
    15.
    发明授权
    Sense amplifier of a memory cell 有权
    存储单元的感应放大器

    公开(公告)号：US09460759B2

    公开(公告)日：2016-10-04

    申请号：US14149353

    申请日：2014-01-07

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Mihail Jefremow

    IPC: G11C7/12 ,  G11C7/06 ,  G11C11/16 ,  G11C13/00 ,  G11C16/26

    CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C16/26

    Abstract: A sense amplifier of a memory cell having a sense voltage generating circuit configured to generate a sense voltage; and a sensing circuit configured to compare a bitline voltage of the memory cell with the sense voltage, and to output a digital output signal indicating a content of the memory cell, wherein during a sense phase, the sensing circuit is decoupled from a voltage supply which charges a bitline capacitance during a precharge phase, and is coupled to and supplied by the bitline capacitance. The sense voltage generating circuit may be further configured to generate a sense voltage that during a precharge phase is dependent on the voltage supply and during a sense phase is independent of the voltage supply.

    Abstract translation: 具有感测电压发生电路的存储单元的读出放大器被配置为产生检测电压; 以及感测电路，被配置为将存储器单元的位线电压与感测电压进行比较，并且输出指示存储器单元的内容的数字输出信号，其中在感测阶段期间，感测电路与电压源 在预充电阶段期间对位线电容充电，并且被位线电容耦合并由位线电容提供。 感测电压产生电路还可以被配置为产生在预充电阶段期间取决于电压供应并且在感测阶段期间独立于电压供应的感测电压。

    Method, apparatus and device for data processing
    16.
    发明授权
    Method, apparatus and device for data processing 有权
    用于数据处理的方法，装置和装置

    公开(公告)号：US09196320B2

    公开(公告)日：2015-11-24

    申请号：US14106277

    申请日：2013-12-13

    Applicant: Infineon Technologies AG

    Inventor： Thomas Kern ,  Mihail Jefremow

    IPC: G11C7/00

    CPC classification number: G11C7/00 ,  G11C7/1006 ,  G11C7/1069 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C16/28 ,  G11C2013/0042

    Abstract: An embodiment relates to a method for data processing and comprises determining an electrical variable for each cell of a data bit, transforming each electrical variable into the time domain, and determining a blank state for at least one data bit based on a comparison of the transformed electrical variables.

    Abstract translation: 一个实施例涉及一种用于数据处理的方法，包括：确定数据位的每个单元的电变量，将每个电变量变换成时域，以及根据变换后的变量的比较确定至少一个数据位的空白状态 电气变量。

    MEMORY READOUT CIRCUIT
    17.
    发明申请
    MEMORY READOUT CIRCUIT 有权

    公开(公告)号：US20250037745A1

    公开(公告)日：2025-01-30

    申请号：US18782285

    申请日：2024-07-24

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Thomas Kern ,  Arndt Voigtlander

    IPC: G11C7/10 ,  G11C7/22

    Abstract: One embodiment describes a memory readout circuit. The memory readout circuit includes a readout node having a capacitance that is discharged by the memory cell to read out a memory cell by means of a cell current, a level detector that is configured to provide a digital output signal and to switch over the output signal when the potential of the readout node (due to the discharge of the readout node) crosses a switching threshold (depending on the selection of the level and the polarity downward or upward, that is to say the switching threshold is overshot or undershot), and a control circuit that is configured to set the switching threshold and/or the switching speed of the level detector depending on the cell current.

    RESOLVER-TO-DIGITAL CONVERSION WITH ROTATION SPEED OFFSET
    18.
    发明公开
    RESOLVER-TO-DIGITAL CONVERSION WITH ROTATION SPEED OFFSET 审中-公开

    公开(公告)号：US20240213898A1

    公开(公告)日：2024-06-27

    申请号：US18069307

    申请日：2022-12-21

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Jürgen Schäfer ,  Michael Augustin ,  Chandresh Patel ,  Arndt Voigtländer

    IPC: H02P21/10 ,  H02P21/09

    CPC classification number: H02P21/10 ,  H02P21/09

    Abstract: A resolver-to-digital converter, comprising: a feedback (FB) filter chain loop having a state observer configured to estimate a rotation speed and a rotation angle of an object, based on a pair of input sine and cosine signals that are amplitude-modulated (AM) to correspond with the rotation angle of the object; and a feedforward (FF) filter chain path configured to estimate the rotation speed of the object based on the pair of input sine and cosine signals, wherein the state observer of the FB filter chain loop is further configured to offset the estimated rotation speed of the FB filter chain loop with the estimated rotation speed of the FF filter chain path to decrease a settling time of the estimated rotation angle.

    TIME MEASUREMENT OF A CLOCK-BASED SIGNAL
    20.
    发明申请
    TIME MEASUREMENT OF A CLOCK-BASED SIGNAL 有权

    公开(公告)号：US20220085824A1

    公开(公告)日：2022-03-17

    申请号：US17467767

    申请日：2021-09-07

    Applicant: Infineon Technologies AG

    Inventor： Mihail Jefremow ,  Ketan Dewan ,  Rex Kho ,  Ralph Mueller-Eschenbach ,  Juergen Schaefer

    IPC: H03M1/12 ,  G06F1/10 ,  G01R31/317

    Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

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