公开(公告)号：US09263422B2

公开(公告)日：2016-02-16

申请号：US14599245

申请日：2015-01-16

Applicant: Intel Corporation

Inventor： Guido Droege ,  Niklas Linkewitsch ,  Andre Schaefer

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L23/48 ,  G11C5/06 ,  G11C7/10 ,  G11C5/04

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

公开(公告)号：US20150108660A1

公开(公告)日：2015-04-23

申请号：US14588183

申请日：2014-12-31

Applicant: Intel Corporation

Inventor： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC: H01L25/065 ,  G11C5/06 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract translation: 具有提供偏移互连的接口的堆叠存储器。 存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。 每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。 每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

公开(公告)号：US09472249B2

公开(公告)日：2016-10-18

申请号：US14829306

申请日：2015-08-18

Applicant: Intel Corporation

Inventor： Andre Schaefer ,  Jen-Chieh Yeh ,  Pei-Wen Luo

IPC: G11C8/00 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4076 ,  G11C8/12 ,  G11C8/10 ,  G11C11/4096 ,  G11C11/4063 ,  G11C11/4097

CPC classification number: G11C7/1072 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/107 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.

公开(公告)号：US20150317228A1

公开(公告)日：2015-11-05

申请号：US14739941

申请日：2015-06-15

Applicant: INTEL CORPORATION

Inventor： Tsun Ho LIU ,  Andre Schaefer ,  Hoi M. Ng ,  Guy R. Murray ,  Oleg Mikulchenko ,  Xiaofang Gao

IPC: G06F11/30 ,  G11C11/406 ,  G06F11/34 ,  G11C11/4096

Abstract: A mechanism is described for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems according to one embodiment of the invention. A method of embodiments of the invention includes monitoring movements of a valid data eye associated with a memory device of a plurality of memory devices of a memory system at a computing system. The monitoring may include initiating write commands during one or more refresh periods associated with the valid data eye. The method may include determining drifting in the movement of the data eye, and correcting the drifting based on adjusting one or more existing phase interpolator values associated with the movements of the data eye.

Abstract translation: 描述了根据本发明的一个实施例的用于促进对跟踪在存储器系统中的不同热条件下的数据眼动的写跟踪的机制。 本发明的实施例的方法包括监视与计算系统处的存储器系统的多个存储器件的存储器件相关联的有效数据眼睛的移动。 监视可以包括在与有效数据眼睛相关联的一个或多个刷新周期期间启动写入命令。 该方法可以包括确定数据眼的运动中的漂移，以及基于调整与数据眼的运动相关联的一个或多个现有的相位内插器值来校正漂移。

公开(公告)号：US09135982B2

公开(公告)日：2015-09-15

申请号：US14133028

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Andre Schaefer ,  Jen-Chieh Yeh ,  Pei-Wen Luo

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/4076 ,  G11C8/12 ,  G11C8/10

CPC classification number: G11C7/1072 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1066 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/107 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.

Abstract translation: 公开了用于访问动态随机存取存储器（DRAM）阵列的示例。 在一些示例中，DRAM存储体的子阵列可以响应于相同的列地址选通而打开多个页面。 在其他示例中，DRAM组的子阵列可以被布置为使得输入/输出（IO）位可以通过IO线以串行方式路由。 对于这些其他示例，IO线可以通过包括DRAM组的DRAM裸片和/或可以耦合到DRAM裸片外部的存储器通道或总线。 其他的例子被描述和要求保护。

公开(公告)号：US08959271B2

公开(公告)日：2015-02-17

申请号：US13835864

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Andre Schaefer

IPC: G06F13/14 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/10 ,  G11C7/109 ,  G11C11/4076

Abstract: A close proximity memory arrangement maintains a point to point association between DQs, or data lines, to DRAM modules employs a clockless state machine on a DRAM side of the memory controller-DRAM interface such that a single FIFO on the memory controller side synchronizes or orders the DRAM fetch results. Addition of a row address (ROW-ADD) and column address (COL-ADD) strobe reducing latency and power demands. Close proximity point to point DRAM interfaces render the DRAM side FIFO redundant in interfaces such as direct stacked 3D DRAMs on top of the logic die hosting the memory controller. The close proximity point to point arrangement eliminates the DRAM internal FIFO and latency scheme, resulting in just the memory controller internal clock domain crossing FIFOs.

Abstract translation: 紧密接近存储器布置保持DQ或数据线之间的点对点关联，DRAM模块在存储器控制器-DRAM接口的DRAM侧采用无时钟状态机，使得存储器控制器侧的单个FIFO同步或命令 DRAM提取结果。 添加行地址（ROW-ADD）和列地址（COL-ADD）选通可以减少延迟和功耗。 接近点到点DRAM接口使得DRAM侧FIFO在诸如直接堆叠的3D DRAM之类的接口中冗余，这些存储器位于托管存储器控制器的逻辑管芯之上。 紧密的点对点布置消除了DRAM内部FIFO和延迟方案，导致内存控制器内部时钟域跨越FIFO。