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公开(公告)号：US09496633B1
公开(公告)日：2016-11-15
申请号：US14746411
申请日：2015-06-22
Applicant: Intel Corporation
Inventor： Shaowu Huang , Beom-Taek Lee
CPC classification number: H01R33/92 , G06F1/185 , G11C5/04 , H01R12/737 , H01R25/00 , H05K1/14 , H05K1/141 , H05K7/1422 , H05K2201/10159 , H05K2201/10189
Abstract: Apparatuses and processes associated with a dual in-line memory module (DIMM) adaptor card. Specifically, the DIMM adaptor card may be configured to removeably couple with a slot of a printed circuit board (PCB). The DIMM adaptor card may further be configured to removeably couple with a first DIMM and a second DIMM. Other embodiments may be described and/or claimed.
Abstract translation: 与双列直插存储器模块（DIMM）适配器卡相关联的设备和过程。 具体来说，DIMM适配器卡可以被配置为可移除地与印刷电路板（PCB）的槽连接。 DIMM适配器卡还可以被配置成可拆卸地与第一DIMM和第二DIMM耦合。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20160276091A1
公开(公告)日：2016-09-22
申请号：US14664827
申请日：2015-03-21
Applicant: INTEL CORPORATION
Inventor： Zhichao Zhang , Gong Ouyang , Kai Xiao , Kemal Aygun , Beom-Taek Lee
CPC classification number: H01F27/2804 , H01F41/041 , H01F2027/2809 , H05K1/0233 , H05K1/0243 , H05K1/0251 , H05K1/165
Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.
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公开(公告)号：US20160174373A1
公开(公告)日：2016-06-16
申请号：US14567402
申请日：2014-12-11
Applicant: Intel Corporation
Inventor： Beom-Taek Lee , Raul Enriquez Shibayama
CPC classification number: H05K1/115 , H01R12/585 , H01R12/718 , H01R31/06 , H05K1/147 , H05K1/184 , H05K2201/10295 , H05K2201/10356 , H05K2201/10378 , H05K2201/10545 , H05K2201/1059 , H05K2201/10704 , H05K2201/10901
Abstract: In one embodiment, the apparatus comprises: a substrate having a first side and a second side, the second side being on an opposite side of the substrate from the first side, where the substrate has a first location on the first side at which an semiconductor package is to be coupled; and a cable coupled to the substrate on the second side of the substrate at a second location on the second side, the second location being at least partially below the first location.
Abstract translation: 在一个实施例中，该装置包括：具有第一侧和第二侧的衬底，第二侧与衬底的与第一侧相反的一侧，其中衬底在第一侧上具有第一位置， 包装要耦合; 以及在所述第二侧上的第二位置处耦合到所述衬底的所述第二侧上的所述衬底的电缆，所述第二位置至少部分地位于所述第一位置的下方。
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公开(公告)号：US20210399764A1
公开(公告)日：2021-12-23
申请号：US17463976
申请日：2021-09-01
Applicant: Intel Corporation
Inventor： Jingbo Li , Beom-Taek Lee , Jong-Ru Guo , Yunhui Chu , Chunfei Ye , Kai Xiao
Abstract: An apparatus comprises a crosstalk cancelation circuit comprising a plurality of taps to output signals based on a signal transmitted via a first data line; and a summation circuit to combine a signal received by a second data line with the signals output by the plurality of taps to reduce near-end crosstalk present in the signal received by the second data line.
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15.发明授权公开(公告)号：US10477684B2
公开(公告)日：2019-11-12
申请号：US14866637
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Raul Enriquez Shibayama , Beom-Taek Lee , Carolina Garcia Robles
Abstract: Techniques and mechanisms for facilitating connection between a packaged device and a substrate of another device. In an embodiment, a device—such as a printed circuit board—comprises a substrate and a hardware interface at a first side of the substrate, the hardware interface to couple the device to a package including integrated circuitry. The device is further configured to couple to a bridge device via contacts disposed at a second side of the substrate. An interconnect extends from the hardware interface to one of the contacts at the second side. In another embodiment, coupling the substrate to the bridge device interconnects two of the contacts at the second side to one another via the bridge device, where one or more contacts of the hardware interface (e.g., only a subset of all such contacts) are also interconnected with the bridge device via the second side.
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Patent Agency Ranking
公开(公告)号：US09806392B2
公开(公告)日：2017-10-31
申请号：US14716101
申请日：2015-05-19
Applicant: Intel Corporation
Inventor： Shaowu Huang , Hanqiao Zhang , Kai Xiao , Beom-Taek Lee , John J. Abbott , Gary Charles
CPC classification number: H01P3/081 , H04B3/32 , H05K1/02 , H05K1/0219 , H05K1/0233 , H05K3/3452 , H05K9/0022 , H05K2201/083
Abstract: Apparatuses and methods associated with shield lines, and/or complementary decoupling capacitors and/or electromagnetic absorbing materials are disclosed herein. In embodiments, an apparatus may include a substrate having a ground plane; and a first and a second transmission line disposed on the substrate. Further, the apparatus may include a shield line constituted with electromagnetic absorbing material disposed between the first and second transmission lines and not coupled with the ground plane. In embodiments, the substrate may further include a power plane having a plurality of edges and a plurality of spacing; a plurality of decoupling capacitors disposed on the power or ground plane; and electromagnetic absorbing materials adhered to the plurality of edges and disposed in the plurality of spacing. Other embodiments may be described and/or claimed.
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公开(公告)号：US09750129B2
公开(公告)日：2017-08-29
申请号：US15265704
申请日：2016-09-14
Applicant: Intel Corporation
Inventor： Shaowu Huang , Kai Xiao , Beom-Taek Lee , Boping Wu , Xiaoning Ye
IPC: H01P1/24 , H01P1/26 , H01P11/00 , H01P3/08 , H01R12/73 , H01R13/6461 , H05K1/02 , H05K1/18 , H05K3/22 , H05K3/40 , G06F1/16 , H05K1/09 , H01P5/16 , H04L25/03 , H05K3/30
CPC classification number: H05K1/023 , G06F1/16 , H01P1/268 , H01P3/08 , H01P5/16 , H01P11/003 , H01R12/737 , H01R13/6461 , H04L25/03006 , H05K1/0216 , H05K1/0231 , H05K1/0243 , H05K1/0246 , H05K1/0268 , H05K1/09 , H05K1/181 , H05K3/22 , H05K3/303 , H05K3/4007 , H05K2201/10159 , H05K2201/10204
Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
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公开(公告)号：US20170063013A1
公开(公告)日：2017-03-02
申请号：US15291993
申请日：2016-10-12
Applicant: Intel Corporation
Inventor： Shaowu Huang , Beom-Taek Lee
CPC classification number: H01R33/92 , G06F1/185 , G11C5/04 , H01R12/737 , H01R25/00 , H05K1/14 , H05K1/141 , H05K7/1422 , H05K2201/10159 , H05K2201/10189
Abstract: Apparatuses and processes associated with a dual in-line memory module (DIMM) adaptor card. Specifically, the DIMM adaptor card may be configured to removeably couple with a slot of a printed circuit board (PCB). The DIMM adaptor card may further be configured to removeably couple with a first DIMM and a second DIMM. Other embodiments may be described and/or claimed.
Abstract translation: 与双列直插存储器模块（DIMM）适配器卡相关联的设备和过程。 具体来说，DIMM适配器卡可以被配置为可移除地与印刷电路板（PCB）的槽连接。 DIMM适配器卡还可以被配置成可拆卸地与第一DIMM和第二DIMM耦合。 可以描述和/或要求保护其他实施例。
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19.发明申请CROSSTALK, POWER SUPPLY NOISE AND/OR EMI REDUCTION METHODS AND APPARATUSES 有权CROSSTALK，电源噪声和/或EMI降低方法和装置公开(公告)号：US20160344085A1
公开(公告)日：2016-11-24
申请号：US14716101
申请日：2015-05-19
Applicant: Intel Corporation
Inventor： Shaowu Huang , Hanqiao Zhang , Kai Xiao , Beom-Taek Lee , John J. Abbott , Gary Charles
CPC classification number: H01P3/081 , H04B3/32 , H05K1/02 , H05K1/0219 , H05K1/0233 , H05K3/3452 , H05K9/0022 , H05K2201/083
Abstract: Apparatuses and methods associated with shield lines, and/or complementary decoupling capacitors and/or electromagnetic absorbing materials are disclosed herein. In embodiments, an apparatus may include a substrate having a ground plane; and a first and a second transmission line disposed on the substrate. Further, the apparatus may include a shield line constituted with electromagnetic absorbing material disposed between the first and second transmission lines and not coupled with the ground plane. In embodiments, the substrate may further include a power plane having a plurality of edges and a plurality of spacing; a plurality of decoupling capacitors disposed on the power or ground plane; and electromagnetic absorbing materials adhered to the plurality of edges and disposed in the plurality of spacing. Other embodiments may be described and/or claimed.
Abstract translation: 本文公开了与屏蔽线和/或互补去耦电容器和/或电磁吸收材料相关联的装置和方法。 在实施例中，装置可以包括具有接地平面的基板; 以及设置在基板上的第一和第二传输线。 此外，该装置可以包括由设置在第一和第二传输线之间并且不与接地平面耦合的电磁吸收材料构成的屏蔽线。 在实施例中，基板还可以包括具有多个边缘和多个间隔的电力平面; 设置在电源或接地平面上的多个去耦电容器; 和电磁吸收材料粘附到多个边缘并以多个间隔设置。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20160179733A1
公开(公告)日：2016-06-23
申请号：US14580950
申请日：2014-12-23
Applicant: Intel Corporation
Inventor： Shaowu Huang , Beom-Taek Lee
CPC classification number: G06F13/4072 , G06F1/183 , G06F13/28 , G06F13/4282 , H01R12/7076 , H01R12/716 , H01R12/721 , H01R13/502 , H05K1/025 , H05K3/366 , H05K2201/10159 , H05K2201/10189
Abstract: A two-part electrical connector includes a bottom connector and a top connector. The bottom connector includes a set of electrical contacts, at least one of which has a relatively short effective electrical stub length. The bottom connector may be mounted on a memory bus that also includes a standard memory receiver. In such a system, when driving by a memory bus, the bottom connector generates signal reflections that are significantly reduced compared to conventional systems.
Abstract translation: 两部分电连接器包括底部连接器和顶部连接器。 底部连接器包括一组电触点，其中至少一个具有相对较短的有效电插脚长度。 底部连接器可以安装在也包括标准存储器接收器的存储器总线上。 在这种系统中，当通过存储器总线驱动时，底部连接器产生与常规系统相比显着降低的信号反射。
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