公开(公告)号：US20230178513A1

公开(公告)日：2023-06-08

申请号：US17543419

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel A. Elsherbini ,  Christopher M. Pelto ,  Georgios Dogiamis ,  Bradley A. Jackson ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/50 ,  H01L24/80 ,  H01L24/96 ,  H01L24/16 ,  H01L2225/06572 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.

公开(公告)号：US09850121B2

公开(公告)日：2017-12-26

申请号：US14949470

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Christopher M. Pelto

IPC: H01L29/84 ,  B81B7/00 ,  B81C1/00 ,  B81B7/02 ,  B81B3/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: B81B7/0006 ,  B81B3/0021 ,  B81B7/02 ,  B81C1/00246 ,  B81C2203/0771 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L29/84 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.

公开(公告)号：US09530740B2

公开(公告)日：2016-12-27

申请号：US14836828

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.