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    Rounded metal trace corner for stress reduction
    12.
    发明授权
    Rounded metal trace corner for stress reduction 有权

    公开(公告)号：US11380643B2

    公开(公告)日：2022-07-05

    申请号：US17009321

    申请日：2020-09-01

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

    EMIB COPPER LAYER FOR SIGNAL AND POWER ROUTING
    13.
    发明申请
    EMIB COPPER LAYER FOR SIGNAL AND POWER ROUTING 有权

    公开(公告)号：US20210296240A1

    公开(公告)日：2021-09-23

    申请号：US16319647

    申请日：2016-09-12

    Applicant: Intel Corporation

    Inventor： Yidnekachew S. Mekonnen ,  Dae-Woo Kim ,  Kemal Aygun ,  Sujit Sharan

    IPC: H01L23/538 ,  H01L21/48

    Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.

    Projecting contacts and method for making the same
    14.
    发明授权
    Projecting contacts and method for making the same 有权

    公开(公告)号：US10978423B2

    公开(公告)日：2021-04-13

    申请号：US15781998

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Ravindranath V. Mahajan

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L29/66 ,  H01L29/40 ,  H01L23/58

    Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.

    Metal-free frame design for silicon bridges for semiconductor packages
    15.
    发明授权
    Metal-free frame design for silicon bridges for semiconductor packages 有权

    公开(公告)号：US10461047B2

    公开(公告)日：2019-10-29

    申请号：US15749744

    申请日：2015-10-29

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

    IPC: H01L23/538 ,  H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

    INTERCONNECT ROUTING CONFIGURATIONS AND ASSOCIATED TECHNIQUES
    17.
    发明申请
    INTERCONNECT ROUTING CONFIGURATIONS AND ASSOCIATED TECHNIQUES 有权
    互连路由配置和相关技术

    公开(公告)号：US20160085899A1

    公开(公告)日：2016-03-24

    申请号：US14491693

    申请日：2014-09-19

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

    IPC: G06F17/50 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538

    CPC classification number: H01L23/5381 ,  G06F17/5077 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例涉及互连路由配置和相关技术。 在一个实施例中，一种装置包括基板，设置在基板上并具有第一多个迹线的第一布线层和与第一布线层直接相邻设置且具有第二多个迹线的第二布线层，其中第一布线层 第一多个迹线的迹线具有大于第二多个迹线的第二迹线的宽度的宽度。 可以描述和/或要求保护其他实施例。

    Rounded metal trace corner for stress reduction
    18.
    发明授权
    Rounded metal trace corner for stress reduction 有权

    公开(公告)号：US10797014B2

    公开(公告)日：2020-10-06

    申请号：US16320680

    申请日：2016-08-16

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

    Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

    Metal-free frame design for silicon bridges for semiconductor packages
    20.
    发明授权
    Metal-free frame design for silicon bridges for semiconductor packages 有权

    公开(公告)号：US12170253B2

    公开(公告)日：2024-12-17

    申请号：US18114123

    申请日：2023-02-24

    Applicant: Intel Corporation

    Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

    IPC: H01L23/538 ,  G01R31/27 ,  H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/544 ,  H01L23/58 ,  H01L23/14 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

    Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

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