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公开(公告)号：US20190155362A1
公开(公告)日：2019-05-23
申请号：US16252012
申请日：2019-01-18
Applicant: Intel Corporation
Inventor： Doron Rajwan , Efraim Rotem , Eliezer Weissmann , Avinash N. Ananthakrishnan , Dorit Shapira
IPC: G06F1/3228 , G06F1/324 , G06F1/3203 , G06F1/3237
Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
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公开(公告)号：US09983644B2
公开(公告)日：2018-05-29
申请号：US14936945
申请日：2015-11-10
Applicant: Intel Corporation
Inventor： Shmuel Zobel , Maxim Levit , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Dorit Shapira , Nadav Shulman
IPC: G06F1/26
CPC classification number: G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.
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公开(公告)号：US20170131754A1
公开(公告)日：2017-05-11
申请号：US14936945
申请日：2015-11-10
Applicant: Intel Corporation
Inventor： Shmuel Zobel , Maxim Levit , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Dorit Shapira , Nadav Shulman
IPC: G06F1/26
CPC classification number: G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.
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14.发明申请公开(公告)号：US20150377955A1
公开(公告)日：2015-12-31
申请号：US14319197
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Dorit Shapira , Krishnakanth V. Sistla , Efraim Rotem , Eric Distefano , James G. Hermerding, II , Esfir Natanzon
CPC classification number: G06F11/3024 , G01R31/2856 , G06F1/324 , G06F1/3296 , G06F11/3058 , G06F11/3409 , G06F2201/81 , Y02D10/126 , Y02D10/172
Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
Abstract translation: 一种用户可配置可靠性控制回路的装置和方法。 例如，处理器的一个实施例包括：可靠性计量器，用于基于测量的处理器操作条件跟踪处理器的部件上的累积应力; 以及控制器，用于从用户或制造商接收压力限制信息，并且根据累积的应力和应力限制信息响应地在处理器上指定一组N个操作限制; 以及性能选择逻辑，用于基于由控制器指定的N个操作限制来输出处理器的一个或多个实际操作条件。
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公开(公告)号：US11481013B2
公开(公告)日：2022-10-25
申请号：US16880167
申请日：2020-05-21
Applicant: Intel Corporation
Inventor： Doron Rajwan , Efraim Rotem , Eliezer Weissmann , Avinash N. Ananthakrishnan , Dorit Shapira
IPC: G06F15/76 , G06F1/3228 , G06F1/324 , G06F1/3237 , G06F1/3203 , G06F1/3234 , G06F1/3293 , G06F30/34 , G06F119/06 , G06F119/08
Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US11144085B2
公开(公告)日：2021-10-12
申请号：US15632000
申请日：2017-06-23
Applicant: Intel Corporation
Inventor： Asma H. Al-Rawi , Federico Ardanaz , Jonathan M. Eastep , Dorit Shapira , Krishnakanth Sistla , Nikhil Gupta , Vasudevan Srinivasan , Chris MacNamara
Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.
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17.发明授权公开(公告)号：US11029744B2
公开(公告)日：2021-06-08
申请号：US15857802
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Efraim Rotem , Esfir Natanzon , Doron Rajwan , Eliezer Weissmann , Dorit Shapira , Lily P. Looi , Bart Plackle , Nadav Shulman
IPC: G06F1/26 , G06F1/32 , G06F1/324 , G06F1/20 , G06F11/30 , G06F1/3296 , G06F1/3287 , G06F1/3206
Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.
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公开(公告)号：US10289514B2
公开(公告)日：2019-05-14
申请号：US14319197
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Dorit Shapira , Krishnakanth V. Sistla , Efraim Rotem , Eric Distefano , James G. Hermerding, II , Esfir Natanzon
IPC: G06F11/30 , G06F11/34 , G06F1/324 , G06F1/3296 , G01R31/28
Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
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公开(公告)号：US09904339B2
公开(公告)日：2018-02-27
申请号：US14482148
申请日：2014-09-10
Applicant: Intel Corporation
Inventor： Dorit Shapira , Efraim Rotem , Doron Rajwan , Nadav Shulman , Esfir Natanzon , Nir Rosenzweig
CPC classification number: G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.
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公开(公告)号：US09791904B2
公开(公告)日：2017-10-17
申请号：US14461039
申请日：2014-08-15
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Doron Rajwan , Dorit Shapira , Nadav Shulman , Tomer Ziv
CPC classification number: G06F1/206 , G01K1/026 , G01K13/00 , G06F1/3206 , G06F1/3234 , G06F1/324
Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
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