公开(公告)号：US20220093314A1

公开(公告)日：2022-03-24

申请号：US17025537

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Anuj MODI ,  Huong DO ,  William J. LAMBERT ,  Krishna BHARATH ,  Harish KRISHNAMURTHY

IPC: H01F27/24 ,  H01F30/06

Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.

公开(公告)号：US20220102261A1

公开(公告)日：2022-03-31

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F17/00 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20220102055A1

公开(公告)日：2022-03-31

申请号：US17033354

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Krishna BHARATH ,  Haifa HARIRI ,  Tarek A. IBRAHIM

IPC: H01F27/28 ,  H01L23/498 ,  H01L23/64 ,  H01F41/04 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages with embedded inductors and methods of forming such electronic packages. In an embodiment, the electronic package comprises a package core, and a plated through hole (PTH) through a thickness of the package core. In an embodiment, the electronic package further and a magnetic shell around a perimeter of the PTH, where a height of the magnetic shell is less than the thickness of the package core. In an embodiment, the magnetic shell comprises a substantially vertical sidewall and a bottom surface that is tapered.

公开(公告)号：US20210104475A1

公开(公告)日：2021-04-08

申请号：US16596328

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Krishna BHARATH ,  Clive HENDRICKS

IPC: H01L23/64 ,  H01F17/00 ,  H01F17/04 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments include an inductor, a method to form the inductor, and a semiconductor package. An inductor includes a plurality of plated-through-hole (PTH) vias in a substrate layer, and a plurality of magnetic interconnects with a plurality of openings in the substrate layer. The openings of the magnetic interconnects surround the PTH vias. The inductor also includes an insulating layer in the substrate layer, a first conductive layer over the PTH vias, magnetic interconnects, and insulating layer, and a second conductive layer below the PTH vias, magnetic interconnects, and insulating layer. The insulating layer surrounds the PTH vias and magnetic interconnects. The magnetic interconnects may have a thickness substantially equal to a thickness of the PTH vias. The magnetic interconnects may be shaped as hollow cylindrical magnetic cores with magnetic materials. The magnetic materials may include ferroelectric, conductive, or epoxy materials. The hollow cylindrical magnetic cores may be ferroelectric cores.

公开(公告)号：US20200235449A1

公开(公告)日：2020-07-23

申请号：US16841072

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H01P3/06 ,  H01P3/02 ,  H05K1/02 ,  H01P3/08

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20180226310A1

公开(公告)日：2018-08-09

申请号：US15748138

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Feras EID ,  Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Yidnekachew MEKONNEN ,  Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Aleksandar ALEKSOV ,  Nathan FRITZ

IPC: H01L23/14 ,  H01L21/48 ,  H01L23/473 ,  H01L23/538 ,  H01L23/492

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/4871 ,  H01L23/12 ,  H01L23/473 ,  H01L23/492 ,  H01L23/5389

Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.