公开(公告)号：US20180158933A1

公开(公告)日：2018-06-07

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Matthew V. METZ ,  Willy RACHMADY ,  Marc C. FRENCH ,  Jack T. KAVALIEROS ,  Rafael RIOS ,  Seiyon KIM ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  James M. POWERS ,  Sherry R. TAFT

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20180151702A1

公开(公告)日：2018-05-31

申请号：US15576251

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Gopinath BHIMARASETTI ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02546 ,  H01L23/49827 ,  H01L23/49838 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20180151684A1

公开(公告)日：2018-05-31

申请号：US15576253

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Scott B. CLENDENNING ,  Jack T. KAVALIEROS

IPC: H01L29/45 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66568 ,  H01L29/78

Abstract: An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

公开(公告)号：US20200066326A1

公开(公告)日：2020-02-27

申请号：US15776058

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Rafael RIOS ,  Gilbert DEWEY ,  Van H. LE ,  Jack KAVALIEROS ,  Mesut METERELLIYOZ

IPC: G11C11/4097 ,  G11C11/405 ,  H01L27/108

Abstract: A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

公开(公告)号：US20190131437A1

公开(公告)日：2019-05-02

申请号：US16095655

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Van Hoang LE ,  Gilbert William DEWEY ,  Marko RADOSAVLJEVIC ,  Rafael RIOS ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/24

Abstract: Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

公开(公告)号：US20190131187A1

公开(公告)日：2019-05-02

申请号：US16094452

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Van H. LE ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Rafael RIOS ,  Gilbert DEWEY

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L23/522

Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20180366587A1

公开(公告)日：2018-12-20

申请号：US15777117

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20180122901A1

公开(公告)日：2018-05-03

申请号：US15859226

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20170133462A1

公开(公告)日：2017-05-11

申请号：US15410649

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  B82Y10/00 ,  H01L27/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20160373108A1

公开(公告)日：2016-12-22

申请号：US15122150

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Rafael RIOS ,  Ian A. YOUNG

IPC: H03K17/693 ,  H01L29/775 ,  G11C5/06 ,  H01L27/092

CPC classification number: H03K17/693 ,  G11C5/066 ,  H01L27/092 ,  H01L29/7391 ,  H01L29/775 ,  H03K19/094 ,  H03K19/0948

Abstract: Multiplexor circuits with Tunneling field effect transistors (TFET) devices are described. For example, a multiplexor circuit includes a first set of tunneling field effect transistor (TFET) devices that are coupled to each other. The first set of TFET devices receive a first data input signal, a first select signal, and a second select signal. A second set of TFET devices are coupled to each other and receive a second data input signal, the first select signal, and the second select signal. An output terminal is coupled to the first and second set of TFETs. The output terminal generates an output signal of the multiplexor circuit.

Abstract translation: 描述了具有隧道场效应晶体管（TFET）器件的多路复用器电路。 例如，多路复用器电路包括彼此耦合的第一组隧道场效应晶体管（TFET）器件。 第一组TFET器件接收第一数据输入信号，第一选择信号和第二选择信号。 第二组TFET器件彼此耦合并且接收第二数据输入信号，第一选择信号和第二选择信号。 输出端子耦合到第一和第二组TFET。 输出端产生多路复用器电路的输出信号。