公开(公告)号：US20190034360A1

公开(公告)日：2019-01-31

申请号：US15660819

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Kaushik VAIDYANATHAN ,  Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG ,  Tanay KARNIK ,  Huichu LIU

IPC: G06F13/10 ,  G06F9/445 ,  G06F1/26

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20160373108A1

公开(公告)日：2016-12-22

申请号：US15122150

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Rafael RIOS ,  Ian A. YOUNG

IPC: H03K17/693 ,  H01L29/775 ,  G11C5/06 ,  H01L27/092

CPC classification number: H03K17/693 ,  G11C5/066 ,  H01L27/092 ,  H01L29/7391 ,  H01L29/775 ,  H03K19/094 ,  H03K19/0948

Abstract: Multiplexor circuits with Tunneling field effect transistors (TFET) devices are described. For example, a multiplexor circuit includes a first set of tunneling field effect transistor (TFET) devices that are coupled to each other. The first set of TFET devices receive a first data input signal, a first select signal, and a second select signal. A second set of TFET devices are coupled to each other and receive a second data input signal, the first select signal, and the second select signal. An output terminal is coupled to the first and second set of TFETs. The output terminal generates an output signal of the multiplexor circuit.

Abstract translation: 描述了具有隧道场效应晶体管（TFET）器件的多路复用器电路。 例如，多路复用器电路包括彼此耦合的第一组隧道场效应晶体管（TFET）器件。 第一组TFET器件接收第一数据输入信号，第一选择信号和第二选择信号。 第二组TFET器件彼此耦合并且接收第二数据输入信号，第一选择信号和第二选择信号。 输出端子耦合到第一和第二组TFET。 输出端产生多路复用器电路的输出信号。

公开(公告)号：US20210020233A1

公开(公告)日：2021-01-21

申请号：US17061272

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US20170345496A1

公开(公告)日：2017-11-30

申请号：US15164665

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Daniel H. MORRIS ,  Sasikanth MANIPATRUNI ,  Kaushik VAIDYANATHAN ,  Ian A. YOUNG ,  Tanay KARNIK

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

Abstract: An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to be coupled to the select line during a first mode and to be de-coupled during a second mode.

公开(公告)号：US20190027211A1

公开(公告)日：2019-01-24

申请号：US16078582

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: G11C11/412 ,  G11C11/419 ,  G11C8/16 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C8/16 ,  G11C11/223 ,  G11C11/419 ,  H01L27/11

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US20190013063A1

公开(公告)日：2019-01-10

申请号：US16079400

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Sasikanth MANIPATRUNI ,  Daniel H. MORRIS ,  Kaushik VAIDYANATHAN ,  Niloy MUKHERJEE ,  Dmitri E. NIKONOV ,  Ian YOUNG ,  Tanay KARNIK

IPC: G11C11/413 ,  G11C11/412 ,  G11C13/00 ,  G11C14/00 ,  G11C7/10

CPC classification number: G11C11/413 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/20 ,  G11C11/412 ,  G11C13/0007 ,  G11C14/009 ,  G11C2213/70 ,  G11C2213/71

Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

公开(公告)号：US20200118616A1

公开(公告)日：2020-04-16

申请号：US16732951

申请日：2020-01-02

Applicant: Intel Corporation

Inventor： Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  G11C8/16

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US20190243662A1

公开(公告)日：2019-08-08

申请号：US16384715

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Vaidyanathan KAUSHIK ,  Daniel H. MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG ,  Tanay KARNIK ,  Huichi LIU

IPC: G06F9/445 ,  G06F1/26 ,  H03K19/0185

CPC classification number: G06F9/445 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/4411 ,  H03K19/018585

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US20180151578A1

公开(公告)日：2018-05-31

申请号：US15576269

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Uygar E. AVCI ,  Daniel H. MORRIS ,  Ian A. YOUNG ,  Stephen M. RAMEY

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L27/11526 ,  H01L27/02 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/788 ,  H01L29/7881

Abstract: Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.

公开(公告)号：US20200321446A1

公开(公告)日：2020-10-08

申请号：US16635739

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Uygar E. AVCI ,  Joshua M. HOWARD ,  Ian A. YOUNG ,  Daniel H. MORRIS

IPC: H01L29/66 ,  H01L29/51

Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side