公开(公告)号：US11157064B2

公开(公告)日：2021-10-26

申请号：US15719276

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy ,  Ramamurthy Krithivas ,  Vivek Garg ,  Venkatesh Ramamurthy

IPC: G06F1/3287 ,  G06F1/28 ,  G06F1/26

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.

公开(公告)号：US10956351B2

公开(公告)日：2021-03-23

申请号：US16566576

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley Burres ,  Pawel Szymanski ,  Yi-Feng Liu

IPC: G06F13/364 ,  G06F13/40 ,  G06F9/4401 ,  G06F9/445

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US09703697B2

公开(公告)日：2017-07-11

申请号：US13728608

申请日：2012-12-27

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Palsamy Sakthikumar

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  Y02D10/13

Abstract: Methods and apparatus related to sharing Serial Peripheral Interface (SPI) flash memory in a multi-node server SoC (System on Chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of System on Chip (SoC) devices. Each of the plurality of SoC devices comprises controller logic to control access to the multi-port non-volatile memory and/or to translate a host referenced address of a memory access request to a linear address space and a physical address space of the multi-port non-volatile memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US09686143B2

公开(公告)日：2017-06-20

申请号：US14494892

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC: H04L12/24 ,  H04L29/12 ,  H04L12/855

CPC classification number: H04L41/12 ,  H04L41/044 ,  H04L47/2466 ,  H04L61/2015 ,  H04L61/2507

Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

公开(公告)号：US20160147291A1

公开(公告)日：2016-05-26

申请号：US14554384

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多芯片封装（MCP）的第一芯片。 第一芯片包括至少一个核心和第一芯片温度控制（TC）逻辑，以响应于第一芯片的第一芯片温度超过第一阈值的指示来在MCP的第二芯片处断言第一功率调整信号。 处理器还包括导管，其包括将第一芯片耦合到MCP内的第二芯片的双向引脚。 导管将第一功率调整信号从第一芯片传输到第二芯片，第一功率调整信号将引起第二芯片的第二芯片功率消耗的调整。 描述和要求保护其他实施例。

公开(公告)号：US20190087610A1

公开(公告)日：2019-03-21

申请号：US15984699

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Donald C. Soltis, JR. ,  Bradley Burres

IPC: G06F21/88 ,  G06F21/44 ,  G06F21/74 ,  G06F21/72 ,  G06F8/60

Abstract: An integrated circuit (IC) provisioned for asset protection has a primary circuit portion, such as a microprocessor or system-on-chip, that can be selectively disabled and enabled via an operability control input. The IC includes a secure register to store lock state indicia and unlock criteria, where a signal at the operability control input is responsive to the lock state indicia. In operation, a firmware data store receives and stores firmware code that includes a lock/unlock command, and firmware data that includes an unlock key. An authorization module verifies authenticity of the firmware code. A lock/unlock (LUL) module is operative to write lock state indicia to the secure register based on the lock/unlock command only in response to a positive verification of the authenticity of the firmware code by the authorization module, and to write lock state indicia to the secure register.

公开(公告)号：US10223161B2

公开(公告)日：2019-03-05

申请号：US15432826

申请日：2017-02-14

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Balaji Parthasarathy

IPC: G06F3/00 ,  G06F13/00 ,  G06F9/50 ,  G06F9/445 ,  G06F9/4401 ,  G06F13/12 ,  G06F1/26 ,  G06F9/54

Abstract: The present disclosure is directed to hardware-based inter-device resource sharing. For example, a remote orchestrator (RO) may provide instructions to cause a device to make at least one hardware resource available to other devices. An RO module in the device may interact with the RO and may configure a configuration module in the device based on instructions received from the RO. The configuration module may set a device configuration when the device transitions from a power off state to a power on state. The device may also comprise a processing module to process data based on the device configuration, interface technology (IT) and at least one hardware resource. The interface technology may allow the processing module and the at least one hardware resource to interact. The RO module may configure the IT to allow the at least one hardware resource to operate locally or remotely based on the instructions.

公开(公告)号：US10222823B2

公开(公告)日：2019-03-05

申请号：US14750159

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Thane M. Larson ,  Ramamurthy Krithivas ,  Chris Ruffin

IPC: G06F1/14 ,  G06F9/4401 ,  G06F1/3203

Abstract: The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a real time clock (RTC) coupled to a bus, where the RTC does not have a backup power source to maintain time and date of the RTC. The computing apparatus may have firmware coupled to the bus, and the firmware may contain boot logic with network time protocol (NTP) logic. The computing apparatus may have persistent memory coupled to the bus with configuration parameters. The computing apparatus may have a controller coupled to the bus, where the controller is to retrieve the configuration parameters from the persistent memory and processes the boot logic with the NTP logic using the configuration parameters to transmit an NTP request over the bus and receives a coordinated universal time (UTC) over the bus and stores the UTC in the RTC.

公开(公告)号：US20160378135A1

公开(公告)日：2016-12-29

申请号：US14750159

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Thane M. Larson ,  Ramamurthy Krithivas ,  Chris Ruffin

IPC: G06F1/14 ,  G06F9/44

CPC classification number: G06F1/14 ,  G06F1/3203 ,  G06F9/4401

Abstract: The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a real time clock (RTC) coupled to a bus, where the RTC does not have a backup power source to maintain time and date of the RTC. The computing apparatus may have firmware coupled to the bus, and the firmware may contain boot logic with network time protocol (NTP) logic. The computing apparatus may have persistent memory coupled to the bus with configuration parameters. The computing apparatus may have a controller coupled to the bus, where the controller is to retrieve the configuration parameters from the persistent memory and processes the boot logic with the NTP logic using the configuration parameters to transmit an NTP request over the bus and receives a coordinated universal time (UTC) over the bus and stores the UTC in the RTC.

Abstract translation: 本公开描述了与具有耦合到总线的实时时钟（RTC）的计算装置相关的装置和方法的实施例，其中RTC没有备用电源来维持RTC的时间和日期。 计算设备可以具有耦合到总线的固件，并且固件可以包含具有网络时间协议（NTP）逻辑的引导逻辑。 计算设备可以具有通过配置参数耦合到总线的持久存储器。 计算设备可以具有耦合到总线的控制器，其中控制器将从持久存储器检索配置参数，并使用配置参数使用NTP逻辑处理引导逻辑，以通过总线发送NTP请求，并且接收协调 通用时间（UTC），并将UTC存储在RTC中。

公开(公告)号：US11874787B2

公开(公告)日：2024-01-16

申请号：US16790648

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Amit K Srivastava ,  Majid Shushtarian ,  Anand K Enamandram ,  Jared W Havican ,  Jeffrey A Pihlman ,  Michael J Karas ,  Ramamurthy Krithivas ,  Christine Watnik

IPC: G06F13/40 ,  G06F9/4401

CPC classification number: G06F13/4063 ,  G06F9/4403 ,  G06F9/4418

Abstract: Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH. The multi-socket platforms include a platform with a bootable CPU coupled to one or more non-legacy CPUs and employing multiple IO-expanders and platform with a legacy CPU coupled to one or more non-legacy CPUs and coupled to a legacy PCH, and further including one or more PCHs coupled to the non-legacy CPU(s) implemented as IO-expanders.