公开(公告)号：US12014081B2

公开(公告)日：2024-06-18

申请号：US17122158

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Anoop Mukker ,  Shankar Natarajan ,  Romesh Trivedi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

公开(公告)号：US11500446B2

公开(公告)日：2022-11-15

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Shankar Natarajan ,  Chang Wan Ha ,  Chee Law ,  Khaled Hasnat ,  Chuan Lin ,  Shafqat Ahmed

IPC: G06F1/32 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G06F1/3234

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

公开(公告)号：US20210141703A1

公开(公告)日：2021-05-13

申请号：US17133834

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/20 ,  G06F1/30 ,  G06F16/22

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US10379782B2

公开(公告)日：2019-08-13

申请号：US15680435

申请日：2017-08-18

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Sriram Natarajan ,  Shankar Natarajan ,  Jason B. Akers

IPC: G06F3/06 ,  G06F12/0893

Abstract: Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.

公开(公告)号：US20190056886A1

公开(公告)日：2019-02-21

申请号：US15680435

申请日：2017-08-18

Applicant: Intel Corporation

Inventor： Suresh Nagarajan ,  Sriram Natarajan ,  Shankar Natarajan ,  Jason B. Akers

IPC: G06F3/06 ,  G06F12/0893

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/202

Abstract: Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.

公开(公告)号：US09626531B2

公开(公告)日：2017-04-18

申请号：US14543935

申请日：2014-11-18

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Jason Cox ,  Charles B. Foster ,  Hinesh K. Shah

IPC: G06F12/14 ,  G06F21/78 ,  G06F21/62 ,  G11B20/00 ,  G06F21/60 ,  G06F21/00 ,  H04L9/32

CPC classification number: G06F21/78 ,  G06F21/604 ,  G06F21/6245 ,  G06F2212/402 ,  G06F2221/2111 ,  G11B20/0021

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for secure control of access control enablement and activation on self-encrypting storage devices. In some embodiments, the device may include a non-volatile memory (NVM) and a secure access control module. The secure access control module may include a command processor module configured to receive a request to enable access controls of the NVM from a user, and to enable the access controls. The secure access control module may also include a verification module configured to verify a physical presence of the user. The secure access control module may further include an encryption module to encrypt at least a portion of the NVM in response to an indication of success from the verification module.

公开(公告)号：US11769557B2

公开(公告)日：2023-09-26

申请号：US16715791

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Arun Sitaram Athreya ,  Shankar Natarajan ,  Sriram Natarajan ,  Yihua Zhang ,  Suresh Nagarajan

IPC: G11C16/04 ,  G11C16/34 ,  G06F3/06 ,  G11C16/26 ,  G11C11/56 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0688 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

公开(公告)号：US11119672B2

公开(公告)日：2021-09-14

申请号：US16532870

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Shivashekar Muralishankar ,  Sriram Natarajan ,  Yihua Zhang

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G06F12/02

Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

公开(公告)号：US11099760B2

公开(公告)日：2021-08-24

申请号：US15842799

申请日：2017-12-14

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Ning Wu

IPC: G06F3/06 ,  G11C16/34 ,  G06F16/11 ,  G06F16/174 ,  G11C16/26 ,  G11C29/52 ,  G11C16/04 ,  G11C16/10 ,  G06F11/10

Abstract: Techniques for performing background refresh for storage devices using a timestamp from the host are described. In one example, a method involves receiving a timestamp from a host, storing the timestamp in a storage device, and determining a retention time for data stored in one or more blocks of the storage device based on the timestamp relative to a second timestamp indicating when the data was written to the one or more blocks. In response to determining the retention time exceeds a threshold, the storage device moves the data to one or more other blocks of the storage device, which can include interleaving the refresh writes with activity from the host.

公开(公告)号：US20200167089A1

公开(公告)日：2020-05-28

申请号：US16532870

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Shivashekar Muralishankar ,  Sriram Natarajan ,  Yihua Zhang

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.