公开(公告)号：US20230317676A1

公开(公告)日：2023-10-05

申请号：US17711926

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Feras Eid ,  Wenhao Li ,  Zhaozhi Li ,  Pilin Liu

IPC: H01L23/00 ,  B23K20/02

CPC classification number: H01L24/75 ,  H01L24/81 ,  B23K20/023 ,  H01L2224/05647 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/75983 ,  H01L2224/75984 ,  H01L2224/75985 ,  H01L2224/75312 ,  H01L2224/75252 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/75253 ,  B23K2101/40

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) assembly including a bond head with a first thermal zone separated from a second thermal zone by a thermal separator, the thermal separator extending through a thickness of the bond head. A bond head nozzle is coupled to a first side of the bond head, where the bond head nozzle includes one or more nozzle channels extending through a thickness of the bond head nozzle.

公开(公告)号：US20230317675A1

公开(公告)日：2023-10-05

申请号：US17711925

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Michael Baker ,  Zhaozhi Li ,  Feras Eid ,  Pilin Liu ,  Wenhao Li

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L2224/81203 ,  H01L2224/75983 ,  H01L2224/75252

Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) tool including a pedestal having a convex surface to receive a package substrate, a bond head to compress a die against the package substrate, and a heat source thermally coupled to at least one of the pedestal or the bond head.

公开(公告)号：US20230317630A1

公开(公告)日：2023-10-05

申请号：US17710502

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Michael Baker ,  Pilin Liu ,  Zhaozhi Li

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/81203

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.

公开(公告)号：US20230285999A1

公开(公告)日：2023-09-14

申请号：US17694302

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Wenhao Li ,  Feras Eid ,  Paul Diglio ,  Jiraporn Seangatith

IPC: B05B7/14 ,  B05B7/16

CPC classification number: B05B7/1486 ,  B05B7/1626

Abstract: Cold-spray nozzles, systems, and techniques are described herein related to manufacturing implementations of efficient film deposition. A deposition system includes multiple feed systems to deliver solid powder materials at controlled feed rates and temperatures, and a nozzle, including convergent and divergent sections and connections to the feed systems, to receive a carrier fluid in the convergent section and to spray the carrier fluid and the solid powder materials out of the divergent section. A nozzle includes multiple ports to receive solid powder materials for admission into a carrier fluid, with one or more ports in the convergent section and one or more ports in the divergent section. A method may include delivering a carrier fluid to a nozzle, heating multiple solid powder materials, delivering these solid powder materials to the nozzle, and spraying the solid powder materials out of a divergent section of the nozzle.

公开(公告)号：US20230099827A1

公开(公告)日：2023-03-30

申请号：US17484281

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Wenhao Li ,  Stephen Morein ,  Yoshihiro Tomita

IPC: H01L23/532 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20240063066A1

公开(公告)日：2024-02-22

申请号：US17891665

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Tomita Yoshihiro ,  Adel A. Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi ,  Yi Shi ,  Batao Zhang ,  Wenhao Li ,  Feras Eid

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/46 ,  H01L23/367

CPC classification number: H01L23/041 ,  H01L25/0652 ,  H01L23/18 ,  H01L24/08 ,  H01L23/481 ,  H01L23/46 ,  H01L23/367 ,  H01L2224/08145 ,  H01L2224/05599 ,  H01L24/05 ,  H01L2224/80379 ,  H01L24/80 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/131 ,  H01L24/13 ,  H01L2224/29099 ,  H01L24/29

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

公开(公告)号：US20230317545A1

公开(公告)日：2023-10-05

申请号：US17710507

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Pilin Liu ,  Feras Eid ,  Michael Baker ,  Wenhao Li ,  Zhaozhi Li

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L23/367 ,  H01L24/16 ,  H01L24/17 ,  H01L24/08 ,  H01L24/09 ,  H01L24/81 ,  H01L23/3732 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2224/81203 ,  H01L2224/10155 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2224/16014 ,  H01L2224/16013 ,  H01L2224/16057 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17132 ,  H01L2224/17133 ,  H01L2224/0801 ,  H01L2224/0903 ,  H01L2224/09104 ,  H01L2224/08113

Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

公开(公告)号：US20230282543A1

公开(公告)日：2023-09-07

申请号：US17685063

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Feras Eid ,  Wenhao Li ,  Yoshihiro Tomita

IPC: H01L23/373

CPC classification number: H01L23/3733

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein that has a graded content to reduce the coefficient of thermal expansion at the backside surface of the integrated circuit device. The filler material may have at least two filler material particle constituents having different particle diameters, wherein a first filler material particle constituent that has the smaller average diameter is closest to the backside surface of the integrated circuit device and wherein a second filler material constituent that has the larger average diameter is farthest from the backside surface of the integrated circuit device.

公开(公告)号：US20230098710A1

公开(公告)日：2023-03-30

申请号：US17484329

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Aleksandar Aleksov ,  Feras Eid ,  Adel Elsherbini ,  Wenhao Li ,  Stephen Morein

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230098303A1

公开(公告)日：2023-03-30

申请号：US17484339

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Aleksandar Aleksov ,  Feras Eid ,  Adel Elsherbini ,  Wenhao Li ,  Stephen Morein

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.