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    MEMS DEVICE AND PROCESS FOR RF AND LOW RESISTANCE APPLICATIONS
    12.
    发明申请
    MEMS DEVICE AND PROCESS FOR RF AND LOW RESISTANCE APPLICATIONS 审中-公开

    公开(公告)号：US20170297900A1

    公开(公告)日：2017-10-19

    申请号：US15477193

    申请日：2017-04-03

    Applicant: INVENSENSE, INC.

    Inventor： Michael J. DANEMAN ,  Martin LIM ,  Xiang LI ,  Li-Wen HUNG

    IPC: B81B3/00 ,  B81C3/00

    CPC classification number: B81B3/0086 ,  B81B2207/07 ,  B81C3/001 ,  B81C2201/019

    Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.

    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL
    14.
    发明申请
    METHOD OF INCREASING MEMS ENCLOSURE PRESSURE USING OUTGASSING MATERIAL 有权
    使用外加材料增加MEMS外壳压力的方法

    公开(公告)号：US20170001861A1

    公开(公告)日：2017-01-05

    申请号：US15265668

    申请日：2016-09-14

    Applicant: InvenSense, Inc.

    Inventor： Cerina ZHANG ,  Martin LIM ,  Jongwoo SHIN ,  Joseph SEEGER

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

    Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二基板和第一基板彼此接合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

    CMOS-MEMS-CMOS PLATFORM
    15.
    发明申请
    CMOS-MEMS-CMOS PLATFORM 有权
    CMOS-MEMS-CMOS平台

    公开(公告)号：US20160362293A1

    公开(公告)日：2016-12-15

    申请号：US14738745

    申请日：2015-06-12

    Applicant: InvenSense, Inc.

    Inventor： Peter SMEYS ,  Martin LIM

    IPC: B81B7/00

    CPC classification number: B81B7/007 ,  B81B2201/0207 ,  B81B2201/0214 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2203/0315 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00012

    Abstract: A sensor chip combining a substrate comprising at least one CMOS circuit, a MEMS substrate and another substrate comprising at least one CMOS circuit in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first substrate with a first surface and a second surface comprising at least one CMOS circuit; a MEMS substrate with a first surface and a second surface; and a second substrate comprising at least one CMOS circuit. Where the first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the MEMS substrate. The second surface of the MEMS substrate is attached to the second substrate. The first substrate, the MEMS substrate, the second substrate and the packaging substrate are mechanically attached and provided with electrical inter-connects.

    Abstract translation: 公开了一种传感器芯片，其组合包括至少一个CMOS电路，MEMS基板和包括垂直堆叠的一个封装中的至少一个CMOS电路的另一基板的基板。 所述封装包括传感器芯片，还包括具有第一表面的第一基板和包括至少一个CMOS电路的第二表面; 具有第一表面和第二表面的MEMS衬底; 以及包括至少一个CMOS电路的第二衬底。 其中第一衬底的第一表面附接到封装衬底，并且第一衬底的第二表面附接到MEMS衬底的第一表面。 MEMS基板的第二表面附接到第二基板。 第一基板，MEMS基板，第二基板和封装基板机械地连接并设置有电连接。

    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE
    16.
    发明申请
    CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE 有权
    CMOS-MEMS集成器件，其中包括在不同的控制压力下的多个CAVIITY和制造方法

    公开(公告)号：US20150129991A1

    公开(公告)日：2015-05-14

    申请号：US14603185

    申请日：2015-01-22

    Applicant: InvenSense, Inc.

    Inventor： Daesung LEE ,  Jongwoo SHIN ,  Jong Il SHIN ,  Peter SMEYS ,  Martin LIM

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/0023 ,  B81B7/0038 ,  B81B7/0041 ,  B81B7/02 ,  B81B2201/0228 ,  B81B2207/017 ,  B81C1/00285 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0785

    Abstract: An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer.

    Abstract translation: 集成MEMS器件包括两个基板，其中第一和第二基板耦合在一起并且其间具有两个外壳。 第一和第二基板之一包括除气源层和去气阻挡层，以调节两个外壳内的压力。 该方法包括在基板上沉积和图案化除气源层和第一除气阻挡层，产生两个横截面。 在两个横截面之一中，除气源层的顶表面不被除气阻挡层覆盖，而在两个横截面中的另一个中，除气源层被封装在除气阻挡层中。 该方法还包括平行地沉积第二除气阻挡层并蚀刻第二除气阻挡层，使得第二除气阻挡层的间隔物留在除气源层的侧壁上。

    INTERNAL ELECTRICAL CONTACT FOR ENCLOSED MEMS DEVICES
    17.
    发明申请
    INTERNAL ELECTRICAL CONTACT FOR ENCLOSED MEMS DEVICES 有权
    用于封装的MEMS器件的内部电气接点

    公开(公告)号：US20140349434A1

    公开(公告)日：2014-11-27

    申请号：US14456973

    申请日：2014-08-11

    Applicant: InvenSense, Inc.

    Inventor： Kegang HUANG ,  Jongwoo SHIN ,  Martin LIM ,  Michael Julian DANEMAN ,  Joseph SEEGER

    IPC: B81C1/00

    CPC classification number: B81C1/00301 ,  B81B7/0064 ,  B81B2207/098 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/031

    Abstract: A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

    Abstract translation: 公开了一种在集成MEMS器件中制造电连接的方法。 该方法包括形成MEMS晶片。 形成MEMS晶片包括在第一半导体层中形成一个空腔，将第一半导体层与设置在第一半导体层和第二半导体层之间的电介质层结合到第二半导体层，并且通过第二半导体蚀刻至少一个通孔 层和介电层，并在第二半导体层上沉积导电材料并填充至少一个通孔。 形成MEMS晶片还包括图案化和蚀刻导电材料以形成一个间隔并在导电材料上沉积锗层，图案化和蚀刻锗层，以及图案化和蚀刻第二半导体层以限定一个MEMS结构。 该方法还包括将MEMS晶片接合到基底基板。

    MEMS DEVICE AND PROCESS FOR RF AND LOW RESISTANCE APPLICATIONS
    18.
    发明申请
    MEMS DEVICE AND PROCESS FOR RF AND LOW RESISTANCE APPLICATIONS 审中-公开

    公开(公告)号：US20180312394A1

    公开(公告)日：2018-11-01

    申请号：US15477202

    申请日：2017-04-03

    Applicant: INVENSENSE, INC.

    Inventor： Michael J. DANEMAN ,  Martin LIM ,  Xiang LI ,  Li-Wen HUNG

    IPC: B81B3/00 ,  B81C3/00

    CPC classification number: B81B3/0086 ,  B81B2207/07 ,  B81C3/001 ,  B81C2201/019

    Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.

    CAVITY PRESSURE MODIFICATION USING LOCAL HEATING WITH A LASER
    20.
    发明申请
    CAVITY PRESSURE MODIFICATION USING LOCAL HEATING WITH A LASER 有权
    使用本地加热激光的气压改进

    公开(公告)号：US20160325985A1

    公开(公告)日：2016-11-10

    申请号：US14705630

    申请日：2015-05-06

    Applicant: InvenSense, Inc.

    Inventor： Michael DUEWEKE ,  Martin LIM

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81B7/0038 ,  B81B7/02 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00285 ,  B81C1/00293 ,  B81C2201/0161 ,  B81C2203/0785

    Abstract: A method and system for changing a pressure within at least one enclosure in a MEMS device are disclosed. In a first aspect, the method comprises applying a laser through one of the at least two substrates onto a material which changes the pressure within at least one enclosure when exposed to the laser, wherein the at least one enclosure is formed by the at least two substrates. In a second aspect, the system comprises a MEMS device that includes a first substrate, a second substrate bonded to the first substrate, wherein at least one enclosure is located between the first and the second substrates, a metal layer within one of the first substrate and the second substrate, and a material vertically oriented over the metal layer, wherein when the material is heated the material changes a pressure within the at least one enclosure.

    Abstract translation: 公开了一种用于改变MEMS装置中的至少一个外壳内的压力的方法和系统。 在第一方面，所述方法包括将激光通过所述至少两个基板之一施加到当暴露于所述激光器时改变至少一个外壳内的压力的材料，其中所述至少一个外壳由所述至少两个基板形成 底物。 在第二方面，该系统包括MEMS器件，其包括第一衬底，与第一衬底结合的第二衬底，其中至少一个外壳位于第一和第二衬底之间，第一衬底之一内的金属层 和第二基底以及垂直取向在金属层上的材料，其中当材料被加热时，材料改变至少一个外壳内的压力。

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