Abstract:
A MEMS device includes a dual membrane, an electrode, and an interconnecting structure. The dual membrane has a top membrane and a bottom membrane. The bottom membrane is positioned between the top membrane and the electrode and the interconnecting structure defines a spacing between the top membrane and the bottom membrane.
Abstract:
An ultrasonic sensor includes a two-dimensional array of ultrasonic transducers, wherein the two-dimensional array of ultrasonic transducers is substantially flat, a contact layer having a non-uniform thickness overlying the two-dimensional array of ultrasonic transducers, and an array controller configured to control activation of ultrasonic transducers during an imaging operation. During the imaging operation, the array controller is configured to control a transmission frequency of activated ultrasonic transducers during the imaging operation, wherein a plurality of transmission frequencies are used during the imaging operation to account for an impact of an interference pattern caused by the non-uniform thickness of the contact layer, and is configured to capture at least one fingerprint image using the plurality of transmission frequencies.
Abstract:
A piezoelectric micromachined ultrasound transducer (PMUT) device may include a plurality of layers including a structural layer, a piezoelectric layer, and electrode layers located on opposite sides of the piezoelectric layer. Conductive barrier layers may be located between the piezoelectric layer and the electrodes to the prevent diffusion of the piezoelectric layer into the electrode layers.
Abstract:
An electronic device includes a substrate layer having a front surface and a back surface opposite the front surface, a plurality of ultrasonic transducers formed on the front surface of the substrate layer, wherein the plurality of ultrasonic transducers generate backward waves during operation, the backward waves propagating through the substrate layer, and a plurality of substrate structures formed within the back surface of the substrate layer, the plurality of substrate structures configured to modify the backward waves during the operation.
Abstract:
A piezoelectric micromachined ultrasound transducer (PMUT) array may comprise PMUT devices with respective piezoelectric layers and electrode layers. Parasitic capacitance can be reduced when an electrode layer is not shared across PMUT devices but may expose the devices to electromagnetic interference (EMI). A conductive layer located within the structural layer or on a shared plane with the electrode layers may reduce EMI affecting the PMUT array operation.
Abstract:
An ultrasonic sensor includes a two-dimensional array of ultrasonic transducers, a contact layer, a matching layer between the two-dimensional array and the contact layer, where the matching layer has a non-uniform thickness, and an array controller configured to control activation of ultrasonic transducers during an imaging operation for imaging a plurality of pixels within the two-dimensional array of ultrasonic transducers. During the imaging operation, the array controller is configured to activate different subsets of ultrasonic transducers associated with different regions of the two-dimensional array of ultrasonic transducers at different transmission frequencies, where the different frequencies are determined such that a thickness of the matching layer at a region is substantially equal to a quarter wavelength of the first transmission frequency for the region. The array controller is also configured to combine the plurality of pixels into a compound fingerprint image that compensates for the non-uniform thickness of the matching layer.
Abstract:
A piezoelectric micromachined ultrasound transducer (PMUT) array may comprise PMUT devices with respective piezoelectric layers and electrode layers. Parasitic capacitance can be reduced when an electrode layer is not shared across PMUT devices but may expose the devices to electromagnetic interference (EMI). A conductive layer located within the structural layer or on a shared plane with the electrode layers may reduce EMI affecting the PMUT array operation.
Abstract:
A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.
Abstract:
A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.