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20 条记录 (耗时 0.037 秒)

    Multi-element memory device with power control for individual elements
    15.
    发明授权
    Multi-element memory device with power control for individual elements 有权
    具有单个元件功率控制的多元件存储器件

    公开(公告)号：US09256279B2

    公开(公告)日：2016-02-09

    申请号：US14127886

    申请日：2012-06-12

    申请人： Deborah Lindsey Dressler ,  Julia Kelly Cline ,  Wayne Frederick Ellis

    发明人： Deborah Lindsey Dressler ,  Julia Kelly Cline ,  Wayne Frederick Ellis

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G11C5/06

    CPC分类号： G06F1/28 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/4273 ,  G11C5/063

    摘要： A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

    摘要翻译： 多元件装置包括多个存储器元件，每个存储器元件包括存储器阵列，用于控制对存储器阵列的访问的访问电路和功率控制电路。 包括用于存储第一和第二控制值的一个或多个控制寄存器的功率控制电路根据第一控制值控制对接入电路的功率分配，并且根据第二控制值控制对存储器阵列的功率分配 控制值。 每个存储器元件还包括边带电路，用于使主机系统能够至少设置一个或多个控制寄存器中的第一控制值和第二控制值。

    Multi-port multiple-simultaneous-access DRAM chip
    17.
    发明授权
    Multi-port multiple-simultaneous-access DRAM chip 失效
    多端口多同时访问DRAM芯片

    公开(公告)号：US5875470A

    公开(公告)日：1999-02-23

    申请号：US841029

    申请日：1997-04-29

    申请人： Jeffrey Harris Dreibelbis ,  Wayne Frederick Ellis ,  Thomas James Heller, Jr. ,  Michael Ignatowski ,  Howard Leo Kalter ,  David Meltzer

    发明人： Jeffrey Harris Dreibelbis ,  Wayne Frederick Ellis ,  Thomas James Heller, Jr. ,  Michael Ignatowski ,  Howard Leo Kalter ,  David Meltzer

    IPC分类号： G11C7/10 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097 ,  H01L29/78

    CPC分类号： G11C7/1075 ,  G11C11/4097 ,  G11C7/18 ,  G11C8/12

    摘要： Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system. Each section data bus is comprised of a large number of data lines that transfer data bits in parallel to/from all of DRAM cells in an address-selected row in one of the DRAM banks at a time in each section. The four DRAM section buses in the chip may be transferring data at the same time in independent directions to/from the four chip ports.

    摘要翻译： 在半导体芯片内提供连接到每个区段数据总线的多个内部DRAM阵列。 交叉点开关同时将多段数据总线连接到对应的多个端口寄存器，其在芯片上的多个端口（I / O引脚）和数据总线之间在任一数据方向上并行传输数据，以有效支持 与存储器芯片之间的高端口数据速率。 对于任何部分，数据可以在相关联的端口和对应的端口寄存器之间完全并行地传送，或者数据可以在多个并行比特组中的每个端口与其端口寄存器之间进行复用。 芯片中的每个DRAM组通过芯片中的存储体地址控制与其他DRAM组并行地寻址和访问，该存储器地址控制从计算机系统中的四个处理器接收所有地址请求。 每个部分数据总线包括大量的数据线，其在每个部分中一次一个DRAM存储体中的地址选择行中的/从所有DRAM单元并行传送数据位。 芯片中的四个DRAM部分总线可以在独立的方向上同时向四个芯片端口传送数据。

    Robust commands for timing calibration or recalibration
    18.
    发明授权
    Robust commands for timing calibration or recalibration 有权
    鲁棒的命令用于定时校准或重新校准

    公开(公告)号：US09129666B1

    公开(公告)日：2015-09-08

    申请号：US13590495

    申请日：2012-08-21

    申请人： Wayne S. Richardson ,  Wayne Frederick Ellis ,  Yohan Usthavia Frans ,  Lawrence Lai

    发明人： Wayne S. Richardson ,  Wayne Frederick Ellis ,  Yohan Usthavia Frans ,  Lawrence Lai

    IPC分类号： G11C7/00 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C29/023 ,  G11C29/028

    摘要： A memory device is placed in a mode that redefines the command set used to control the memory device. This may occur either in anticipation of the memory system falling out of calibration, or after it has already fallen out of calibration. The redefined command set is designed such that it may be reliably received by the memory device at the specified rate even if the memory system has fallen out of calibration. The redefined command set is then used to issue command(s) to recalibrate one or more communication links such that they can exchange data, commands, and/or addresses at a specified rate. After recalibration, the memory device is returned to responding to the original command set.

    摘要翻译： 存储器件被放置在重新定义用于控制存储器件的命令集的模式中。 这可能发生在预期的存储器系统脱离校准，或者在它已经脱离校准之后。 重新定义的命令集被设计成即使存储器系统已经脱离校准，也可以以指定的速率被存储器件可靠地接收。 然后，重新定义的命令集用于发出命令以重新校准一个或多个通信链路，使得它们可以以指定的速率交换数据，命令和/或地址。 重新校准后，内存设备将返回以响应原始命令集。

    MULTI-ELEMENT MEMORY DEVICE WITH POWER CONTROL FOR INDIVIDUAL ELEMENTS
    19.
    发明申请
    MULTI-ELEMENT MEMORY DEVICE WITH POWER CONTROL FOR INDIVIDUAL ELEMENTS 有权
    具有个性元素功率控制的多元存储器件

    公开(公告)号：US20140201553A1

    公开(公告)日：2014-07-17

    申请号：US14127886

    申请日：2012-06-12

    申请人： Deborah Lindsey Dressler ,  Julia Kelly Cline ,  Wayne Frederick Ellis

    发明人： Deborah Lindsey Dressler ,  Julia Kelly Cline ,  Wayne Frederick Ellis

    IPC分类号： G06F1/32

    CPC分类号： G06F1/28 ,  G06F1/3275 ,  G06F1/3287 ,  G06F13/4273 ,  G11C5/063

    摘要： A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes side-band circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

    摘要翻译： 多元件装置包括多个存储器元件，每个存储器元件包括存储器阵列，用于控制对存储器阵列的访问的访问电路和功率控制电路。 包括用于存储第一和第二控制值的一个或多个控制寄存器的功率控制电路根据第一控制值控制对接入电路的功率分配，并且根据第二控制值控制对存储器阵列的功率分配 控制值。 每个存储器元件还包括侧带电路，用于使主机系统能够至少设置一个或多个控制寄存器中的第一控制值和第二控制值。

    Memory device with programmable self-refreshing and testing methods therefore
    20.
    发明授权
    Memory device with programmable self-refreshing and testing methods therefore 失效
    因此，具有可编程自刷新和测试方法的存储器件

    公开(公告)号：US5703823A

    公开(公告)日：1997-12-30

    申请号：US435606

    申请日：1995-05-05

    申请人： David Elson Douse ,  Wayne Frederick Ellis ,  Erik Leigh Hedberg

    发明人： David Elson Douse ,  Wayne Frederick Ellis ,  Erik Leigh Hedberg

    IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C29/00 ,  G11C29/02 ,  G11C29/08 ,  G11C29/14 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C29/02

    摘要： A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.

    摘要翻译： 一种用于半导体存储器的可编程自适应刷新电路以及用于非侵入式地编程自刷新率的方法，并且确定地测试用于建立/验证刷新率的自定时刷新电路和用于自刷新的等待状态间隔 操作。 可编程刷新电路包括输出时钟信号的自定时振荡器和输出第一信号模式和第二信号模式的可编程模式发生器。 第一信号模式被馈送到还接收时钟信号的计数器电路。 每当由时钟信号驱动的计数达到对应于可编程模式发生器产生的第一信号模式的数字模式表示时，计数器电路输出信号脉冲。 连接刷新控制逻辑以接收脉冲信号并通过刷新半导体存储器件的存储器阵列的一部分来对其进行响应。 刷新控制逻辑采用第二信号模式来设置自刷新操作的等待状态间隔。 还阐述了用于测试可编程自刷新电路的多种方法。