-
11.发明授权Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process 有权非易失性存储器阵列采用栅极击穿结构，在标准sub 0.35微米CMOS工艺中
公开(公告)号：US6044012A
公开(公告)日：2000-03-28
申请号：US263375
申请日：1999-03-05
CPC分类号： G11C17/16
摘要： A non-volatile memory cell is provided that includes a low voltage CMOS storage transistor having a source region and a drain region that are commonly connected to ground. The low voltage storage transistor is programmed by applying a high programming voltage to its gate, thereby rupturing the gate oxide of the storage transistor. The high programming voltage is applied to the low voltage storage transistor through a high voltage p-channel transistor. The high voltage p-channel transistor has a thicker gate oxide than the storage transistor, thereby enabling the p-channel transistor to withstand higher voltages. The high voltage p-channel transistor also has a higher breakdown voltage than a high voltage n-channel transistor of the same size. Both the low voltage storage transistor and the high voltage p-channel transistor are fabricated in accordance with a standard sub 0.35 micron process. The state of the low voltage storage transistor can be read through the p-channel transistor, or through a dedicated high voltage n-channel transistor. In one embodiment, the programming voltage is generated by a charge pump circuit fabricated in accordance with a standard sub 0.35 micron process. In another embodiment, the decoder circuits that access the non-volatile memory cell use high voltage p-channel transistors to transmit the high programming voltage. Another embodiment of the present invention includes a system-on-a-chip structure that implements the non-volatile memory of the present invention.
摘要翻译： 提供了一种非易失性存储单元，其包括具有共同连接到地的源极区和漏极区的低电压CMOS存储晶体管。 通过向其栅极施加高编程电压来对低电压存储晶体管进行编程，从而破坏存储晶体管的栅极氧化物。 高编程电压通过高压p沟道晶体管施加到低电压存储晶体管。 高压p沟道晶体管具有比存储晶体管更厚的栅极氧化物，从而使得p沟道晶体管能够承受更高的电压。 高压p沟道晶体管也具有比相同尺寸的高电压n沟道晶体管更高的击穿电压。 低电压存储晶体管和高压p沟道晶体管都按照标准的次级0.35微米工艺制造。 低电压存储晶体管的状态可以通过p沟道晶体管或通过专用高压n沟道晶体管来读取。 在一个实施例中，编程电压由根据标准次级0.35微米工艺制造的电荷泵电路产生。 在另一个实施例中，访问非易失性存储单元的解码器电路使用高电压p沟道晶体管来传输高编程电压。 本发明的另一实施例包括实现本发明的非易失性存储器的片上系统结构。
-
公开(公告)号：US07917820B1
公开(公告)日：2011-03-29
申请号：US12123867
申请日：2008-05-20
申请人： Adarsh Pavle , Shahin Toutounchi
发明人： Adarsh Pavle , Shahin Toutounchi
IPC分类号： G01R31/28
CPC分类号： G01R31/318597 , G11C29/32 , G11C2029/0401 , G11C2029/3202
摘要： A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.
摘要翻译： 描述了集成电路（“IC”）的嵌入式核心的测试方法。 IC具有在IC中彼此耦合的硬连线的嵌入式核心和存储器。 该方法包括在嵌入式核心工作时将测试向量写入存储器。 测试向量从存储器输入到嵌入式核心，以模拟到嵌入式核心的扫描链输入。 测试结果从嵌入式核心获得部分响应于测试矢量输入。
-
公开(公告)号：US07219287B1
公开(公告)日：2007-05-15
申请号：US10955560
申请日：2004-09-29
CPC分类号： G01R31/31835 , G01R31/318516 , Y10S707/99953
摘要： A method and apparatus are disclosed that simplify and reduce the time required for detecting faults in a programmable device such as a programmable logic device (PLD) by utilizing fault coverage information corresponding to a plurality of test patterns for the PLD to reduce the set of potential faults. For one embodiment, each test pattern is designated as either passing or failing, the faults that are detectable by at least two failing test patterns and the faults that are not detectable by any passing test patterns are eliminated, and the remaining faults are diagnosed. For another embodiment, the faults detectable by each failing test pattern are diagnosed to generate corresponding fault sets, and the faults not common to the fault sets and not detectable by one or more of the failing test patterns are eliminated.
摘要翻译： 公开了一种方法和装置，其通过利用与PLD的多个测试模式对应的故障覆盖信息来简化和减少检测诸如可编程逻辑器件（PLD）的可编程设备中的故障所需的时间，以减少潜在的电位 故障 对于一个实施例，将每个测试模式指定为通过或失败，可以消除由至少两个故障测试模式可检测的故障，并且消除由任何通过的测试模式无法检测到的故障，并且诊断剩余的故障。 对于另一个实施例，可以诊断每个故障测试模式可检测到的故障以产生相应的故障集，并且消除由一个或多个故障测试模式不能检测到的故障集合不常见的故障。
-
公开(公告)号：US06732309B1
公开(公告)日：2004-05-04
申请号：US09921115
申请日：2001-08-02
申请人： Shahin Toutounchi , Andrew W. Lai
发明人： Shahin Toutounchi , Andrew W. Lai
IPC分类号： G01R3128
CPC分类号： G01R31/318516
摘要： A new method to test short faults in a programmable logic device is described. The line segments under test are connected together to form a conducting chain. All the line segments neighboring to the conducting chain are tied to a known state. A test vector is applied to the programmable logic device. The state of the line under test is measured. If it is the same as the known state, the programmable logic device is likely to have faults.
摘要翻译： 描述了一种在可编程逻辑器件中测试短路故障的新方法。 被测线路连接在一起形成导电链。 与导向链相邻的所有线段被绑定到已知状态。 将测试矢量应用于可编程逻辑器件。 测量被测线路的状态。 如果与已知状态相同，则可编程逻辑器件可能存在故障。
-
15.发明授权Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration 有权内置自检（BIST）技术，用于使用部分重配置测试现场可编程门阵列（FPGA）公开(公告)号：US07302625B1
公开(公告)日：2007-11-27
申请号：US11284455
申请日：2005-11-21
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/3187 , G06F17/5054 , G06F2217/14
摘要： A Built-in Self Test (BIST) system is provided in a Field Programmable Gate Array (FPGA) that can adjust test signal patterns provided for testing after partial reconfiguration of the FPGA. The BIST system includes a decoder that monitors I/O signals and provides an output indicating when I/O signals change indicating partial reconfiguration has occurred. The decoder output is provided to a BIST test signal generator providing signals to an IP core of the FPGA as well as a BIST comparator for monitoring test results to change test signals depending on the partial configuration mode.
摘要翻译： 在现场可编程门阵列（FPGA）中提供了内置自测（BIST）系统，该阵列可以调整FPGA部分重新配置后提供的测试信号模式。 BIST系统包括一个监视I / O信号的解码器，并提供一个输出，指示何时I / O信号变化，表明发生了部分重新配置。 解码器输出提供给BIST测试信号发生器，向FPGA的IP内核提供信号，以及BIST比较器，用于监视测试结果，以根据部分配置模式更改测试信号。
-
公开(公告)号：US06891395B2
公开(公告)日：2005-05-10
申请号：US10853981
申请日：2004-05-25
申请人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
发明人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
IPC分类号： G01R31/28 , G01R31/3185 , G06F17/50 , H01L21/82 , H03K19/173
CPC分类号： G01R31/318519 , G06F17/5054
摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。
-
17.发明授权Radiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereof 失效使用植入P型防护结构的辐射硬化CMOS结构及其制造方法
公开(公告)号：US5220192A
公开(公告)日：1993-06-15
申请号：US911861
申请日：1992-07-10
申请人： Alexander H. Owens , Mike Lyu , Shahin Toutounchi , Abraham Yee
发明人： Alexander H. Owens , Mike Lyu , Shahin Toutounchi , Abraham Yee
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/092 , H01L21/76218 , Y10S257/921 , Y10S438/953
摘要： A radiation hardened NMOS transistor structure suited for application to radiation hardened CMOS devices, and the method for manufacturing it is disclosed. The new transistor structure is characterized by "P" doped guard bands running along and immediately underlying the two bird's beak regions perpendicular to the gate. The transistor and the CMOS structure incorporating it exhibit speed and size comparable to those of conventional non-rad-hard CMOS structure, relatively simple manufacturing, and excellent total-dose radiation hardness.
-
18.发明授权Manufacturing test for a programmable integrated circuit implementing a specific user design 有权实现特定用户设计的可编程集成电路的制造测试公开(公告)号：US08311762B1
公开(公告)日：2012-11-13
申请号：US12885222
申请日：2010-09-17
IPC分类号： G01R27/28
CPC分类号： G01R31/318516
摘要： Methods and systems generate a manufacturing test of a programmable integrated circuit and optionally test the programmable integrated circuit with the manufacturing test. A netlist is generated that represents a specific user design implemented in programmable resources of the programmable integrated circuit. The netlist represents user registers that are implemented in a portion of the logic registers of the programmable logic resources. A virtual scan chain is added to the netlist. Scan-test vectors are generated from the netlist using automatic test pattern generation (ATPG). The scan-test vectors serially scan the portion of the logic registers via the virtual scan chain. The scan-test vectors are converted into access-test vectors that access the portion of the logic registers via a configuration port of the programmable integrated circuit. The programmable integrated circuit is optionally tested for a manufacturing defect with the access-test vectors.
摘要翻译： 方法和系统生成可编程集成电路的制造测试，并可选择地通过制造测试来测试可编程集成电路。 生成一个网表，表示在可编程集成电路的可编程资源中实现的特定用户设计。 网表表示在可编程逻辑资源的逻辑寄存器的一部分中实现的用户寄存器。 虚拟扫描链被添加到网表。 使用自动测试模式生成（ATPG）从网表生成扫描测试向量。 扫描测试向量通过虚拟扫描链顺序扫描逻辑寄存器的一部分。 扫描测试向量被转换成通过可编程集成电路的配置端口访问逻辑寄存器部分的访问测试向量。 可编程集成电路可选择使用访问测试向量测试制造缺陷。
-
19.发明授权Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof 失效集成电路结构包括由图案化氮化物钝化保护的CMOS器件及其制造方法
公开(公告)号：US5561319A
公开(公告)日：1996-10-01
申请号：US298041
申请日：1994-08-30
IPC分类号： H01L23/31 , H01L29/06 , H01L29/40 , H01L29/34 , H01L21/265
CPC分类号： H01L29/408 , H01L23/3171 , H01L2924/0002 , H01L2924/3025 , Y10S438/953 , Y10S438/958
摘要： A CMOS integrated circuit structure is disclosed having a patterned nitride passivation layer, wherein the nitride is patterned such that it does not overlie the thin gate oxide portions of one or more of the MOS devices. When protection against the effects of external radiation is desired, the thin gate oxide areas of the PMOS devices are left uncovered by the patterned nitride passivation layer. When protection is desired against the effects of internally generated "hot electrons", the thin gate oxide areas of the NMOS devices are left uncovered by the patterned nitride passivation layer.
摘要翻译： 公开了具有图案化氮化物钝化层的CMOS集成电路结构，其中图案化氮化物使得其不覆盖一个或多个MOS器件的薄栅极氧化物部分。 当需要防止外部辐射的影响时，PMOS器件的薄栅极氧化物区域被图案化的氮化物钝化层留下。 当需要防止内部产生的“热电子”的影响时，NMOS器件的薄栅极氧化物区域被图案化的氮化物钝化层留下。
-
20.发明授权
公开(公告)号：US5516731A
公开(公告)日：1996-05-14
申请号：US252723
申请日：1994-06-02
IPC分类号： H01L21/324 , H01L21/326 , H01L21/8238 , H01L21/477
CPC分类号： H01L21/326 , H01L21/324 , H01L21/8238 , Y10S438/953
摘要： A technique for improving the radiation hardness and hot-electron resistance of a CMOS integrated circuit is described whereby undesirable hydrogen ions may be vented through any holes, such as contact holes, in an overlying passivation layer by applying an elevated temperature and/or electrical bias to the integrated circuit die. The elevated temperature and electrical bias serve to accelerate the process by which hydrogen vents from the die. The elimination of unwanted hydrogen significantly reduces threshold shifts in the CMOS integrated circuit, providing greater radiation hardness and hot-electron resistance.
摘要翻译： 描述了一种用于提高CMOS集成电路的辐射硬度和热电子电阻的技术，其中不期望的氢离子可以通过施加升高的温度和/或电偏压而在覆盖的钝化层中通过任何孔（例如接触孔）排出 到集成电路管芯。 升高的温度和电气偏压有助于加速从模具排出氢气的过程。 消除不需要的氢显着降低了CMOS集成电路中的阈值偏移，提供更大的辐射硬度和热电阻。
-
-
-
-
-
-
-
-
-
搜索结果
30 条记录 (耗时 0.026 秒)
