公开(公告)号：US5502667A

公开(公告)日：1996-03-26

申请号：US120876

申请日：1993-09-13

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard K. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard K. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： H01L25/18 ,  G11C5/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  G11C5/02

CPC分类号： G11C5/06 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C5/04 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/85207 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19107

摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成多芯片存储器模块结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得以更高级别的存储器芯片的外观定义更强大的存储器架构。 形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得在模块的I / O引脚上出现具有NxM存储器件的单个存储器芯片架构。 在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与包括该子单元的存储器芯片电互连。 控制逻辑芯片的尺寸小于包含子单元的存储器芯片的尺寸。 具有延伸穿过其中的内部开口的引线框固定到电接口层，并且控制逻辑芯片固定到电接口层以便驻留在引线框架内，从而产生致密的多芯片集成电路封装。 相应的制造技术包括促进存储器子单元的侧表面上的金属化图案化的方法。

公开(公告)号：US5517754A

公开(公告)日：1996-05-21

申请号：US252794

申请日：1994-06-02

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

IPC分类号： H01L21/28 ,  H01L21/98 ,  H01L25/065 ,  H05K3/34

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  Y10S269/903 ,  Y10S269/909 ,  Y10S428/914 ,  Y10T29/49124 ,  Y10T29/49144 ,  Y10T428/14 ,  Y10T428/1438 ,  Y10T428/1481 ,  Y10T428/24942

摘要： This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.

摘要翻译： 本发明包括用于在多个单片电子模块上同时形成表面金属化的各种高生产方法。 每个单片电子模块可以包括单个半导体芯片或多个半导体芯片。 该方法可以采用自动中断堆叠中不同电子模块之间的侧面金属化的工件。 多个工件在电子模块之间的堆叠内交错。 每个工件可以包括用于永久地结合到堆叠中的相邻电子模块的端面的转移层。 该转移层可以包括绝缘层，金属化层，有源电路层或其任何组合。 因此，可以同时提供多个电子模块的侧表面金属化的端面金属化。

公开(公告)号：US5596226A

公开(公告)日：1997-01-21

申请号：US301290

申请日：1994-09-06

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Timothy H. Daubenspeck ,  Wayne J. Howell

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Timothy H. Daubenspeck ,  Wayne J. Howell

IPC分类号： H01L25/18 ,  H01L21/02 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L27/00 ,  H01L27/04 ,  H01L23/48

CPC分类号： H01L25/50 ,  H01L24/24 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/14

摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.

摘要翻译： 一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。 制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。 芯片金属化存在于切口区域内。 使用光刻工艺来保护仅暴露切口区域的晶片。 接下来，蚀刻晶片，从切口区域清除芯片金属化。 然后切割晶片，并且将芯片堆叠以形成单片电子模块。 处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。 阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。

公开(公告)号：US5466634A

公开(公告)日：1995-11-14

申请号：US359982

申请日：1994-12-20

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John E. Cronin ,  Wayne J. Howell ,  James M. Leas ,  Robert B. Phillips

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John E. Cronin ,  Wayne J. Howell ,  James M. Leas ,  Robert B. Phillips

IPC分类号： H01L23/538 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/30107

摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.

摘要翻译： 阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。 所述方法包括提供包括多个堆叠的IC芯片的堆叠。 在堆叠上形成侧面薄膜金属化层。 接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。 或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。 所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。 还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

公开(公告)号：US5517057A

公开(公告)日：1996-05-14

申请号：US451356

申请日：1995-05-26

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John E. Cronin ,  Wayne J. Howell ,  James M. Leas ,  Robert B. Phillips

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John E. Cronin ,  Wayne J. Howell ,  James M. Leas ,  Robert B. Phillips

IPC分类号： H01L23/538 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/48 ,  H01L23/522

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/30107

摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.

摘要翻译： 阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。 所述方法包括提供包括多个堆叠的IC芯片的堆叠。 在堆叠上形成侧面薄膜金属化层。 接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。 或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。 所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。 还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

公开(公告)号：US5614277A

公开(公告)日：1997-03-25

申请号：US429992

申请日：1995-04-27

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  Wayne J. Howell

IPC分类号： H01L21/28 ,  H01L21/98 ,  H01L25/065 ,  H05K3/34

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  Y10S269/903 ,  Y10S269/909 ,  Y10S428/914 ,  Y10T29/49124 ,  Y10T29/49144 ,  Y10T428/14 ,  Y10T428/1438 ,  Y10T428/1481 ,  Y10T428/24942

摘要： This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.

摘要翻译： 本发明包括用于在多个单片电子模块上同时形成表面金属化的各种高生产方法。 每个单片电子模块可以包括单个半导体芯片或多个半导体芯片。 该方法可以采用自动中断堆叠中不同电子模块之间的侧面金属化的工件。 多个工件在电子模块之间的堆叠内交错。 每个工件可以包括用于永久地结合到堆叠中的相邻电子模块的端面的转移层。 该转移层可以包括绝缘层，金属化层，有源电路层或其任何组合。 因此，可以同时提供多个电子模块的侧表面金属化的端面金属化。

公开(公告)号：US5567654A

公开(公告)日：1996-10-22

申请号：US313976

申请日：1994-09-28

申请人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John E. Cronin ,  Wayne J. Howell ,  James M. Leas ,  David J. Perlman

发明人： Kenneth E. Beilstein, Jr. ,  Claude L. Bertin ,  John E. Cronin ,  Wayne J. Howell ,  James M. Leas ,  David J. Perlman

IPC分类号： H01L21/98 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L21/60

CPC分类号： H01L25/50 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/30107

摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

摘要翻译： 一种具有附接到侧表面的单独形成的薄膜层的制造方法和所得到的单片电子模块。 该制造方法包括提供由堆叠的集成电路芯片组成的电子模块。 在用于将薄膜层附着到电子模块的临时支架上分开形成薄膜层。 所公开的技术还可以用于将可包括有源电路的插入件附接到电子模块。 阐述了制造方法，所得到的多芯片封装以及各种薄膜结构的具体细节。

公开(公告)号：US6030855A

公开(公告)日：2000-02-29

申请号：US246435

申请日：1999-02-08

申请人： Claude L. Bertin ,  Thomas G. Ference ,  Wayne J. Howell

发明人： Claude L. Bertin ,  Thomas G. Ference ,  Wayne J. Howell

IPC分类号： H01L21/60 ,  H01L21/98 ,  H01L23/485 ,  H01L23/50 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/50 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14

摘要： A semiconductor structure includes a stack of two semiconductor chips. An edge of the chips forms a side surface of the stack. Insulation and adhesive is located between the chips, and a wire contacting circuitry on one of the chips extends through the insulation to the side surface. A first conductor contacts the wire on the side surface. The first conductor is self-aligned to the wire and extends above the side surface. The first conductor facilitates pads or connectors on the side surface that are insulated from the semiconductor chips. The self-aligned first conductor is an electroplated or electroless plated metal.

摘要翻译： 半导体结构包括两个半导体芯片的堆叠。 芯片的边缘形成堆叠的侧表面。 绝缘和粘合剂位于芯片之间，并且其中一个芯片上的导线接触电路通过绝缘体延伸到侧表面。 第一导体接触侧面上的导线。 第一导线与导线自对准并在侧面上方延伸。 第一导体便于侧表面上与半导体芯片绝缘的垫或连接器。 自对准的第一导体是电镀或无电镀金属。

公开(公告)号：US5903045A

公开(公告)日：1999-05-11

申请号：US640379

申请日：1996-04-30

申请人： Claude L. Bertin ,  Thomas G. Ference ,  Wayne J. Howell

发明人： Claude L. Bertin ,  Thomas G. Ference ,  Wayne J. Howell

IPC分类号： H01L21/60 ,  H01L21/98 ,  H01L23/485 ,  H01L23/50 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/50 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14

摘要： A semiconductor structure includes a stack of two semiconductor chips. An edge of the chips forms a side surface of the stack. Insulation and adhesive is located between the chips, and a wire contacting circuitry on one of the chips extends through the insulation to the side surface. A first conductor contacts the wire on the side surface. The first conductor is self-aligned to the wire and extends above the side surface. The first conductor facilitates pads or connectors on the side surface that are insulated from the semiconductor chips. The self-aligned first conductor is an electroplated or electroless plated metal.

公开(公告)号：US5478781A

公开(公告)日：1995-12-26

申请号：US329954

申请日：1994-10-27

申请人： Claude L. Bertin ,  Paul A. Farrar, Sr. ,  Wayne J. Howell ,  Christopher P. Miller ,  David J. Perlman

发明人： Claude L. Bertin ,  Paul A. Farrar, Sr. ,  Wayne J. Howell ,  Christopher P. Miller ,  David J. Perlman

IPC分类号： H01L25/00 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065 ,  H01L21/60

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/09701

摘要： A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

摘要翻译： 堆叠硅半导体芯片的立方体封装。 为了容纳立方体包装，在钝化的芯片表面上添加金属转移层，以将所有表面电触点带到共同的芯片边缘。 金属转移层通过具有低介电常数的聚合物层和与堆叠的芯片的热膨胀系数相匹配的聚合物层与芯片表面和堆叠中的相邻芯片绝缘。 添加粘合剂聚合物层以通过沉积粘合剂层并在晶片级上部分固化来增强第一聚合物层和相邻的芯片之间的结合，然后当芯片堆叠在一起形成时，完全固化 立方体。