公开(公告)号：US20100099936A1

公开(公告)日：2010-04-22

申请号：US12577869

申请日：2009-10-13

申请人： Chae-Ho SHIN ,  Jung-Hyun Park ,  Eunae Noh ,  Kyoungho Row ,  Ji Won Park

发明人： Chae-Ho SHIN ,  Jung-Hyun Park ,  Eunae Noh ,  Kyoungho Row ,  Ji Won Park

IPC分类号： C07C5/333 ,  B01J23/18

CPC分类号： B01J23/8876 ,  B01J23/002 ,  B01J35/0006 ,  B01J35/1009 ,  B01J35/1038 ,  B01J37/03 ,  B01J37/10 ,  B01J2523/00 ,  C07C5/48 ,  C07C2523/18 ,  C07C2523/28 ,  C07C2523/745 ,  C07C11/167 ,  B01J2523/54 ,  B01J2523/68 ,  B01J2523/842

摘要： The present invention relates to a complex oxide catalyst of Bi/Mo/Fe and an oxidative dehydrogenation of 1-butene in the presence of a catalyst herein. A catalyst of the present invention is superior to the conventional Bi/Mo catalyst in thermal and mechanical stabilities, conversion and selectivity toward 1,3-butadiene, while showing a long-term catalytic activity.

摘要翻译： 本发明涉及Bi / Mo / Fe的复合氧化物催化剂和1-丁烯在本文催化剂存在下的氧化脱氢。 本发明的催化剂在热和机械稳定性，转化率和对1,3-丁二烯的选择性方面优于传统的Bi / Mo催化剂，同时显示出长期的催化活性。

公开(公告)号：US20090242238A1

公开(公告)日：2009-10-01

申请号：US12457166

申请日：2009-06-02

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC分类号： H05K1/09

CPC分类号： H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

摘要： A buried pattern substrate includes an insulation layer; a circuit pattern buried in the insulation layer such that a part thereof is exposed at a surface of the insulation layer; and a stud bump buried in the insulation layer such that one end portion is exposed at one surface of the insulation layer, and such that the other end portion is exposed at the other surface of the insulation layer.

摘要翻译： 掩埋图案衬底包括绝缘层; 埋置在绝缘层中的电路图案，使得其一部分在绝缘层的表面露出; 以及埋在所述绝缘层中的螺柱凸起，使得一个端部暴露在所述绝缘层的一个表面处，并且使得所述另一端部暴露在所述绝缘层的另一个表面处。

公开(公告)号：US20090206468A1

公开(公告)日：2009-08-20

申请号：US12385316

申请日：2009-04-03

申请人： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

发明人： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.

摘要翻译： 一种制造片上封装的方法，包括在载体膜上层叠干膜，其一面由薄金属膜层压; 通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; 去除干膜; 层压除了形成焊球垫的部分之外的上光阻焊剂; 蚀刻形成在上层光阻焊层未层叠的部分上的金属薄膜; 通过倒装芯片焊接将半导体芯片安装在焊球垫上; 用钝化材料成型半导体芯片; 去除载体膜和金属薄膜; 并在焊球下方层叠下光阻焊剂。 由于使用种子层形成电路图案，片上封装芯片提供了高密度电路。

公开(公告)号：US20080102410A1

公开(公告)日：2008-05-01

申请号：US11976211

申请日：2007-10-22

申请人： Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

发明人： Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

IPC分类号： G03C5/00

CPC分类号： H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K3/108 ,  H05K3/20 ,  H05K3/4658 ,  H05K3/4697 ,  H05K2203/308 ,  H01L2224/0401

摘要： A method of manufacturing a printed circuit board is disclosed, in which a cavity is formed for embedding a component, which includes: providing a core board, in which an inner circuit is buried; forming a first via in the core board for interlayer conduction; selectively forming a first photoresist in a position on the core board in correspondence with a position of the cavity; stacking a first build-up layer, on which a first outer circuit is formed, on the core board; and selectively removing the first build-up layer in correspondence with the position of the cavity and removing the first photoresist. Utilizing the method, a board can be manufactured with greater precision, as the thickness tolerance of the cavity may be obtained by controlling the thickness of the photoresist, and the overall thickness of the board can be controlled by controlling the height of the cavity.

摘要翻译： 公开了一种制造印刷电路板的方法，其中形成用于嵌入部件的空腔，其包括：提供其中埋入内部电路的芯板; 在芯板中形成层间导电的第一通孔; 在所述芯板上与所述腔的位置对应地选择性地形成第一光致抗蚀剂; 在芯板上堆叠形成有第一外部电路的第一堆积层; 并且与空腔的位置相对应地选择性地去除第一堆积层并除去第一光致抗蚀剂。 利用该方法，可以通过控制光致抗蚀剂的厚度来获得更高精度的板，因为通过控制光致抗蚀剂的厚度可以获得空腔的厚度公差，并且可以通过控制空腔的高度来控制板的整体厚度。

公开(公告)号：USD560627S1

公开(公告)日：2008-01-29

申请号：US29269993

申请日：2006-12-12

申请人： Jung-Hyun Park ,  Hyun-Teak Lim ,  Min-Ho Cha

设计人： Jung-Hyun Park ,  Hyun-Teak Lim ,  Min-Ho Cha

公开(公告)号：USD560182S1

公开(公告)日：2008-01-22

申请号：US29269994

申请日：2006-12-12

申请人： Jung-Hyun Park

设计人： Jung-Hyun Park

公开(公告)号：USD541811S1

公开(公告)日：2007-05-01

申请号：US29241720

申请日：2005-10-31

申请人： Jung-Hyun Park

设计人： Jung-Hyun Park

公开(公告)号：US20070065988A1

公开(公告)日：2007-03-22

申请号：US11524403

申请日：2006-09-21

申请人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC分类号： H01L21/00

CPC分类号： H05K3/4652 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0191 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

摘要： A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second dry film on the first dry film on both sides of the seed layer, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed on both sides of the seed layer, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method for manufacturing a substrate with a cavity in accordance with the present invention can improve the efficiency of a substrate manufacturing process by using both sides of a seed layer to manufacture the substrate with a cavity.

摘要翻译： 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的两侧形成第一电路图案，种子层用于在两侧形成电路图案; （b）在种子层两侧的第一干膜上层叠第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在种子层的两侧上在要形成空腔的区域之外的区域层叠电介质层，电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的用于制造具有空腔的基板的方法可以通过使用种子层的两面来制造具有空腔的基板来提高基板制造工艺的效率。

公开(公告)号：USD530694S1

公开(公告)日：2006-10-24

申请号：US29241719

申请日：2005-10-31

申请人： Jung-Hyun Park

设计人： Jung-Hyun Park

公开(公告)号：US20060145719A1

公开(公告)日：2006-07-06

申请号：US11325145

申请日：2006-01-03

申请人： Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

发明人： Hyeck-Jin Jeong ,  Jung-Hyun Park ,  Heui-Seog Kim ,  Jong-Keun Jeon ,  Seok-Young Yoon

IPC分类号： G01R31/02

CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R1/06722

摘要： A POGO pin that can measure low frequency products as well as RF products and also have a long life span, and a test socket including the POGO pin are provided. The POGO pin includes a metal plunger formed of a conductive metal so as to electrically contact the semiconductor package, and a rubber contact pin connected with the metal plunger and formed of a conductive rubber so as to electrically contact the test board.

摘要翻译： 一个POGO引脚，可以测量低频产品以及RF产品，并且具有较长的使用寿命，并提供包含POGO引脚的测试插座。 POGO针包括由导电金属形成的金属柱塞，以与半导体封装件电接触;以及橡胶触针，与金属柱塞连接并由导电橡胶形成，以便电接触测试板。