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公开(公告)号：US11455209B2
公开(公告)日：2022-09-27
申请号：US17412026
申请日：2021-08-25
Applicant: Kioxia Corporation
Inventor： Takahiro Kubota , Daiki Watanabe , Hironori Uchikawa
Abstract: A memory system includes a non-volatile memory configured to store an N-dimensional error correction code and a memory controller. The memory controller is configured to calculate an ath soft-input value for an ath component code based on correction information of the ath component code (1≤a≤ni) of an ith dimension (1≤i≤N), ath reliability information, and a syndrome value of the ath component code, to calculate a decoded word of the ath component code, the ath correction information, and the ath reliability information by inputting the ath soft-input value and executing a decoding process of the ath component code, to store the ath correction information and bth correction information indicating a corrected position of a bth component code (1≤b≤nj) of a jth dimension (j≠i, 1≤j≤N) in a correction information memory, to store the ath reliability information in a reliability information memory, and to output an output decoded word calculated from the read information and the reliability information of each component code.
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公开(公告)号：US11204831B2
公开(公告)日：2021-12-21
申请号：US16804940
申请日：2020-02-28
Applicant: KIOXIA CORPORATION
Inventor： Yuta Kumano , Hironori Uchikawa
Abstract: A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.
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公开(公告)号：US11711100B2
公开(公告)日：2023-07-25
申请号：US17685981
申请日：2022-03-03
Applicant: KIOXIA CORPORATION
Inventor： Hironori Uchikawa
CPC classification number: H03M13/159 , H03M13/098 , H03M13/1177 , H03M13/1575 , H03M13/2732 , H03M13/2735
Abstract: A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.
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公开(公告)号：US11537465B2
公开(公告)日：2022-12-27
申请号：US17174399
申请日：2021-02-12
Applicant: KIOXIA CORPORATION
Inventor： Tsukasa Tokutomi , Masanobu Shirakawa , Marie Takada , Masamichi Fujiwara , Kazumasa Yamamoto , Naoaki Kokubun , Tatsuro Hitomi , Hironori Uchikawa
Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
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公开(公告)号：US11355202B2
公开(公告)日：2022-06-07
申请号：US16832891
申请日：2020-03-27
Applicant: KIOXIA CORPORATION
Inventor： Noboru Shibata , Hironori Uchikawa
IPC: G11C16/04 , G11C16/26 , H01L27/11582 , H01L27/1157 , G11C8/14 , G11C16/08 , G11C16/10 , G11C7/08
Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
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Patent Agency Ranking
公开(公告)号：US12074616B2
公开(公告)日：2024-08-27
申请号：US18148060
申请日：2022-12-29
Applicant: Kioxia Corporation
Inventor： Shinichi Kanno , Hironori Uchikawa
CPC classification number: H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/29 , H03M13/35 , H03M13/6561 , H03M13/03 , Y02D10/00
Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
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公开(公告)号：US11892907B2
公开(公告)日：2024-02-06
申请号：US17984309
申请日：2022-11-10
Applicant: Kioxia Corporation
Inventor： Tsukasa Tokutomi , Masanobu Shirakawa , Marie Takada , Masamichi Fujiwara , Kazumasa Yamamoto , Naoaki Kokubun , Tatsuro Hitomi , Hironori Uchikawa
CPC classification number: G06F11/1068 , G06F11/1012 , G06F11/1048 , H03M13/1105 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/2906 , H03M13/3715 , H03M13/6505
Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
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公开(公告)号：US11886738B2
公开(公告)日：2024-01-30
申请号：US17887873
申请日：2022-08-15
Applicant: Kioxia Corporation
Inventor： Takahiro Kubota , Hironori Uchikawa , Yuta Kumano
IPC: G06F3/06
CPC classification number: G06F3/0658 , G06F3/0619 , G06F3/0679
Abstract: A memory controller determines the number of pieces of correction information of an a-th correction information for each of M component codes according to a value based on the number of component codes, and determines a correction information address which is an address on a correction information memory of the a-th correction information based on the number of pieces of correction information. The memory controller calculates an a-th soft-input value for an a-th component code, inputting the a-th soft-input value to execute decoding processing of the a-th component code, calculates a decoded word of the a-th component code, a-th correction information, and a-th reliability information, stores the a-th correction information and b-th correction information indicating a b-th corrected location (1≤b≤nj) in a j-th dimension (j≠i, 1≤j≤N) in the correction information address of the correction information memory, stores a-th reliability information in a reliability information memory, and outputs an output decoded word calculated from the read information and the reliability information of each component code.
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公开(公告)号：US11652496B2
公开(公告)日：2023-05-16
申请号：US17463818
申请日：2021-09-01
Applicant: Kioxia Corporation
Inventor： Yuta Kumano , Hironori Uchikawa
CPC classification number: H03M13/1565 , G06F11/1068
Abstract: A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller executes a first decoding process of reading data encoded by an error correction code from the non-volatile memory and repeatedly executing bounded distance decoding on a symbol group protected by each of component codes included in N component code groups; executes a second decoding process of repeatedly executing decoding exceeding a bounded distance in units of component codes for an error symbol group determined to include an error due to a syndrome of a component code included in the N component code groups when the first decoding process fails; executes a rollback process when the first decoding process executed after the second decoding process fails; and changes a parameter used in the second decoding process and further executes the second decoding process when it is detected that the second decoding process is not progressed.
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公开(公告)号：US11011239B2
公开(公告)日：2021-05-18
申请号：US16724100
申请日：2019-12-20
Applicant: KIOXIA CORPORATION
Inventor： Noboru Shibata , Hironori Uchikawa , Taira Shibuya
IPC: G11C11/00 , G11C16/26 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/34 , G06F3/06 , G11C16/32 , H01L27/115
Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
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