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    Semiconductor memory device
    13.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11508697B2

    公开(公告)日：2022-11-22

    申请号：US16806079

    申请日：2020-03-02

    Applicant: Kioxia Corporation

    Inventor： Tomoya Sanuki ,  Hiroshi Maejima ,  Tetsuaki Utsumi

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

    Semiconductor storage device and controller
    14.
    发明授权
    Semiconductor storage device and controller 有权

    公开(公告)号：US11501833B2

    公开(公告)日：2022-11-15

    申请号：US16788639

    申请日：2020-02-12

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi Maejima

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G06F12/02 ,  G11C16/34 ,  G11C11/56 ,  G06F3/06

    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

    Semiconductor storage device
    15.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US11244726B2

    公开(公告)日：2022-02-08

    申请号：US17152355

    申请日：2021-01-19

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi Maejima

    IPC: G11C11/34 ,  G11C16/04 ,  G11C5/06 ,  G11C7/06 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157

    Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

    Semiconductor memory device
    16.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11176998B2

    公开(公告)日：2021-11-16

    申请号：US16883591

    申请日：2020-05-26

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi Maejima

    IPC: G11C16/32 ,  G11C16/04 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

    Memory system, memory controller, and semiconductor memory device
    17.
    发明授权
    Memory system, memory controller, and semiconductor memory device 有权

    公开(公告)号：US11169742B2

    公开(公告)日：2021-11-09

    申请号：US16804037

    申请日：2020-02-28

    Applicant: KIOXIA CORPORATION

    Inventor： Hiroshi Maejima

    IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G06N3/08 ,  G11C16/04

    Abstract: According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.

    Memory device with memory pillar inside conductor
    18.
    发明授权
    Memory device with memory pillar inside conductor 有权

    公开(公告)号：US12159684B2

    公开(公告)日：2024-12-03

    申请号：US17807802

    申请日：2022-06-20

    Applicant: Kioxia Corporation

    Inventor： Hiroshi Maejima ,  Toshifumi Hashimoto

    IPC: G11C7/10 ,  G11C7/08 ,  G11C16/16

    Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.

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