公开(公告)号：US20220301625A1

公开(公告)日：2022-09-22

申请号：US17474904

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Tomoya SANUKI ,  Yasuhito YOSHIMIZU ,  Keisuke NAKATSUKA ,  Hideto HORII ,  Takashi MAEDA

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/10 ,  G11C16/26 ,  G11C5/02 ,  G11C5/06

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

公开(公告)号：US20220204270A1

公开(公告)日：2022-06-30

申请号：US17694532

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: B65G1/137

Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

公开(公告)号：US20210149568A1

公开(公告)日：2021-05-20

申请号：US17121024

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yasuhito YOSHIMIZU ,  Takashi FUKUSHIMA ,  Tatsuro HITOMI ,  Arata INOUE ,  Masayuki MIURA ,  Shinichi KANNO ,  Toshio FUJISAWA ,  Keisuke NAKATSUKA ,  Tomoya SANUKI

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

公开(公告)号：US20210020655A1

公开(公告)日：2021-01-21

申请号：US16801336

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Naoya YOSHIMURA ,  Keisuke NAKATSUKA

IPC: H01L27/11582 ,  G11C7/18 ,  G11C8/14 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view.

公开(公告)号：US20230397417A1

公开(公告)日：2023-12-07

申请号：US18054269

申请日：2022-11-10

Applicant: Kioxia Corporation

Inventor： Masayoshi TAGAMI ,  Keisuke NAKATSUKA

IPC: H01L27/11578 ,  G11C5/06 ,  H01L27/1157

CPC classification number: H01L27/11578 ,  G11C5/063 ,  H01L27/1157

Abstract: A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.

公开(公告)号：US20230320107A1

公开(公告)日：2023-10-05

申请号：US18330779

申请日：2023-06-07

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhiro UCHIYAMA ,  Akira MINO ,  Masayoshi TAGAMI ,  Shinya ARAI

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  G11C16/04 ,  G11C16/26

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  G11C16/0483 ,  G11C16/26 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.

公开(公告)号：US20230075993A1

公开(公告)日：2023-03-09

申请号：US17643263

申请日：2021-12-08

Applicant: Kioxia Corporation

Inventor： Koichi SAKATA ,  Shinya ARAI ,  Susumu HASHIMOTO ,  Akira MINO ,  Shunsuke OKADA ,  Keisuke NAKATSUKA

IPC: H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556

Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a first conductive layer, and a second conductive layer arranged in this order in a first direction and separated from each other, a first semiconductor film extending in the first direction, intersecting the first conductive layer, and being in contact with the second conductive layer, and a first charge storage film arranged between the first semiconductor film and the first conductive layer, and being in contact with the second conductive layer, wherein the first semiconductor film includes a first portion formed of an n-type semiconductor at approximately a same height as the first conductive layer.

公开(公告)号：US20230051013A1

公开(公告)日：2023-02-16

申请号：US17643277

申请日：2021-12-08

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Takuya OHOKA

IPC: H01L27/108

Abstract: In one embodiment, a semiconductor device includes a substrate, transistors on the substrate, and a stacked film provided above the transistors, including electrode layers separated from each other in a first direction, and including first, second and third regions. The device further includes plugs provided to the electrode layers in the first region, a first columnar portion in the second region, and a second columnar portion in the third region. At least one electrode layer among the electrode layers includes a first portion in the first region, a second portion in the second region, and a third portion in the third region, and is a continuous film from the second portion to the third portion via the first portion. The transistors include first, second and third transistors provided right under the first, second and third regions and electrically connected to first, second and third plugs among the plugs, respectively.

公开(公告)号：US20230017909A1

公开(公告)日：2023-01-19

申请号：US17681547

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Daisuke FUJIWARA ,  Toshio FUJISAWA

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097

Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

公开(公告)号：US20220130754A1

公开(公告)日：2022-04-28

申请号：US17438728

申请日：2019-03-19

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhito YOSHIMIZU ,  Tomoya SANUKI ,  Fumitaka ARAI

IPC: H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.