公开(公告)号：US20220173124A1

公开(公告)日：2022-06-02

申请号：US17672819

申请日：2022-02-16

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20240371763A1

公开(公告)日：2024-11-07

申请号：US18639503

申请日：2024-04-18

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H01L23/528 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: According to one embodiment, a semiconductor memory device includes a first chip and a second chip. The first chip includes a plurality of first interconnect layers stacked apart from each other in a first direction, a memory pillar extending in the first direction and passing through the plurality of first interconnect layers, a second interconnect layer electrically coupled to the memory pillar, a first electrode electrically coupled to any one of the plurality of first interconnect layers, and a second electrode electrically coupled to the second interconnect layer. The second chip includes a third electrode bonded to the first electrode, and a fourth electrode bonded to the second electrode. A length of the first electrode in the first direction is larger than a length of the second electrode in the first direction.

公开(公告)号：US12094805B2

公开(公告)日：2024-09-17

申请号：US18079054

申请日：2022-12-12

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Yoshiro Shimojo ,  Shinya Arai

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/481 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US12089410B2

公开(公告)日：2024-09-10

申请号：US18348418

申请日：2023-07-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H10B43/27 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/50

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US11956959B2

公开(公告)日：2024-04-09

申请号：US17328030

申请日：2021-05-24

Applicant: Kioxia Corporation

Inventor： Jun Fujiki ,  Shinya Arai ,  Kotaro Fujii

IPC: H10B43/27 ,  H01L21/768 ,  H01L27/07 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L21/76897 ,  H01L27/0727 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

公开(公告)号：US20230307369A1

公开(公告)日：2023-09-28

申请号：US17890377

申请日：2022-08-18

Applicant: Kioxia Corporation

Inventor： Nobuhito Ichiki ,  Keisuke Nakatsuka ,  Shinya Arai ,  Koichi Sakata ,  Susumu Hashimoto

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/53257 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first wiring, a second wiring, a memory pillar, a semiconductor layer, and a contact plug. The second wiring is provided above the first wiring in a first direction. The memory pillar penetrating at least one of a portion of the first wiring or a portion of the second wiring in the first direction. The semiconductor layer extends in the first direction provided in the memory pillar. The contact plug contains a metal and has a lower surface provided in the memory pillar, and the lower surface is in contact with the semiconductor layer below an upper surface of the second wiring.

公开(公告)号：US11672117B2

公开(公告)日：2023-06-06

申请号：US17143632

申请日：2021-01-07

Applicant: Kioxia Corporation

Inventor： Kotaro Fujii ,  Jun Fujiki ,  Shinya Arai

IPC: H10B43/10 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.

公开(公告)号：US11552000B2

公开(公告)日：2023-01-10

申请号：US17079736

申请日：2020-10-26

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Yoshiro Shimojo ,  Shinya Arai

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US12040314B2

公开(公告)日：2024-07-16

申请号：US17891659

申请日：2022-08-19

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H01L21/50 ,  H01L23/538 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/544

Abstract: A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

公开(公告)号：US11910608B2

公开(公告)日：2024-02-20

申请号：US17961950

申请日：2022-10-07

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H10B43/27 ,  H10B41/27 ,  H10B43/40 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50 ,  G11C16/04 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/225 ,  H01L29/167 ,  H01L21/02 ,  H10B41/41

CPC classification number: H10B43/27 ,  G11C16/14 ,  H01L21/764 ,  H01L29/0649 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/0217 ,  H01L21/2257 ,  H01L21/31116 ,  H01L21/32133 ,  H01L29/167 ,  H10B41/41

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.