公开(公告)号：US6144096A

公开(公告)日：2000-11-07

申请号：US166617

申请日：1998-10-05

申请人： Sergey D. Lopatin

发明人： Sergey D. Lopatin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L24/48

CPC分类号： H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53247 ,  H01L23/53252 ,  H01L2924/0002

摘要： A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with between about 0.2% and 4% tantalum, molybdenum, or tungsten to increase barrier effectiveness and lower resistivity.

摘要翻译： 半导体及其制造方法为具有铜，银或金的导电材料的半导体的具有钴，镍或钯的隔离/粘附层提供。 阻挡层/粘合层可以与约0.2％至4％的钽，钼或钨合金化，以增加屏障效能和降低电阻率。

公开(公告)号：US09567683B2

公开(公告)日：2017-02-14

申请号：US13486202

申请日：2012-06-01

申请人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Robert Z. Bachrach

发明人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Robert Z. Bachrach

IPC分类号： H01M4/64 ,  C25D3/38 ,  C25D5/10 ,  C25D5/18 ,  C25D5/48 ,  C25D17/00 ,  H01M4/04 ,  H01M4/36 ,  H01M4/38 ,  H01M4/66

CPC分类号： C25D3/38 ,  C25D5/10 ,  C25D5/18 ,  C25D5/48 ,  C25D17/00 ,  H01M4/0438 ,  H01M4/366 ,  H01M4/38 ,  H01M4/661

摘要： A method and apparatus for forming a reliable and cost efficient battery or electrochemical capacitor electrode structure that has an improved lifetime, lower production costs, and improved process performance are provided. In one embodiment a method for forming a three dimensional porous electrode for a battery or an electrochemical cell is provided. The method comprises depositing a columnar metal layer over a substrate at a first current density by a diffusion limited deposition process and depositing three dimensional metal porous dendritic structures over the columnar metal layer at a second current density greater than the first current density.

摘要翻译： 提供了一种形成可靠且具有成本效益的电池或电化学电容器电极结构的方法和装置，其具有改善的寿命，降低生产成本和改进的工艺性能。 在一个实施例中，提供了一种用于形成用于电池或电化学电池的三维多孔电极的方法。 该方法包括通过扩散限制沉积工艺以第一电流密度在衬底上沉积柱状金属层，并以大于第一电流密度的第二电流密度在柱状金属层上沉积三维金属多孔树枝状结构。

公开(公告)号：US08486562B2

公开(公告)日：2013-07-16

申请号：US12459313

申请日：2009-06-30

申请人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Robert Z. Bachrach

发明人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Robert Z. Bachrach

IPC分类号： H01M4/60 ,  H01M4/13

CPC分类号： H01M10/0585 ,  C25D1/00 ,  C25D1/006 ,  H01M2/1653 ,  H01M2/1686 ,  H01M4/0428 ,  H01M4/133 ,  H01M4/1393 ,  H01M4/364 ,  H01M4/587 ,  H01M4/667 ,  H01M4/70 ,  H01M6/40 ,  H01M10/0525 ,  H01M10/0565 ,  H01M10/0566 ,  H01M10/058

摘要： A method for forming a battery from via thin-film deposition processes is disclosed. A mesoporous carbon material is deposited onto a surface of a conductive substrate that has high surface area, conductive micro-structures formed thereon. A porous, dielectric separator layer is then deposited on the layer of mesoporous carbon material to form a half cell of an energy storage device. The mesoporous carbon material is made up of CVD-deposited carbon fullerene “onions” and carbon nano-tubes, and has a high porosity capable of retaining lithium ions in concentrations useful for storing significant quantities of electrical energy. Embodiments of the invention further provide for the formation of an electrode having a high surface area conductive region that is useful in a battery structure. In one configuration the electrode has a high surface area conductive region comprising a porous dendritic structure that can be formed by electroplating, physical vapor deposition, chemical vapor deposition, thermal spraying, and/or electroless plating techniques.

摘要翻译： 公开了一种通过薄膜沉积工艺形成电池的方法。 在其上形成有高表面积的导电微结构的导电性基板的表面上沉积介孔碳材料。 然后将多孔介电分离器层沉积在介孔碳材料层上以形成储能装置的半电池。 中孔碳材料由CVD沉积的碳富勒烯“洋葱”和碳纳米管组成，并且具有能够将锂离子保留在用于储存大量电能的浓度的高孔隙率。 本发明的实施例还提供了一种用于电池结构的具有高表面积导电区域的电极的形成。 在一种配置中，电极具有高的表面积导电区域，其包括通过电镀，物理气相沉积，化学气相沉积，热喷涂和/或化学镀技术形成的多孔树枝状结构。

公开(公告)号：US20120064225A1

公开(公告)日：2012-03-15

申请号：US12880564

申请日：2010-09-13

申请人： Robert Z. Bachrach ,  Connie P. Wang ,  Sergey D. Lopatin ,  Hooman Bolandi ,  Ruben Babayants ,  Karl M. Brown ,  Michael C. Kutney

发明人： Robert Z. Bachrach ,  Connie P. Wang ,  Sergey D. Lopatin ,  Hooman Bolandi ,  Ruben Babayants ,  Karl M. Brown ,  Michael C. Kutney

IPC分类号： H01M10/04 ,  B05B5/025 ,  B05C9/14 ,  B05C5/00

CPC分类号： H01M4/0419 ,  H01M10/0404

摘要： In one embodiment, an apparatus for simultaneously depositing an anodically or cathodically active material on opposing sides of a flexible conductive substrate is provided. The apparatus comprises a chamber body defining one or more processing regions in which a flexible conductive substrate is exposed to a dual sided spray deposition process, wherein each of the one or more processing regions are further divided into a first spray deposition region and a second spray deposition region for simultaneously spraying an anodically active or cathodically active material onto opposing sides of a portion of the flexible conductive substrate, wherein each of the first and second spray deposition regions comprise a spray dispenser cartridge for delivering the activated material toward the flexible conductive substrate and a movable collection shutter.

摘要翻译： 在一个实施例中，提供了用于在柔性导电基板的相对侧上同时沉积阳极或阴极活性材料的装置。 该装置包括限定一个或多个处理区域的室主体，其中柔性导电基板暴露于双面喷射沉积工艺，其中一个或多个处理区域中的每一个进一步分为第一喷涂区域和第二喷涂 沉积区域，用于同时将阳极活性或阴极活性材料喷射到柔性导电基底的一部分的相对侧上，其中第一和第二喷射沉积区域中的每一个包括喷射分配器筒，用于将活化材料递送到柔性导电基底， 一个可移动的集合挡板。

公开(公告)号：US20110097628A1

公开(公告)日：2011-04-28

申请号：US12909436

申请日：2010-10-21

申请人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Connie P. Wang ,  Robert Z. Bachrach

发明人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Connie P. Wang ,  Robert Z. Bachrach

IPC分类号： H01M4/38 ,  H01M4/58 ,  H01M4/29 ,  C25D19/00

CPC分类号： H01M4/80 ,  C25D3/32 ,  C25D5/10 ,  C25D7/0614 ,  C25D17/28 ,  H01M4/13 ,  H01M4/139 ,  H01M4/364 ,  H01M4/661 ,  H01M4/666 ,  H01M4/667 ,  H01M4/70 ,  H01M10/0525 ,  H01M10/0566

摘要： Embodiments of the present invention generally relate to lithium-ion batteries, and more specifically, to a system and method for fabricating such batteries using thin-film processes that form three-dimensional structures. In one embodiment, an anodic structure used to form an energy storage device is provided. The anodic structure comprises a flexible conductive substrate, a plurality of conductive microstructures formed on the conductive substrate, comprising a plurality of columnar projections and dendritic structures formed over the plurality of columnar projections and a plurality of tin particles formed on the plurality of conductive microstructures. In another embodiment, the anodic structure further comprises a tin nucleation layer comprising tin particles formed on the flexible conductive substrate between the flexible conductive substrate and the plurality of conductive microstructures.

摘要翻译： 本发明的实施方案一般涉及锂离子电池，更具体地，涉及使用形成三维结构的薄膜工艺制造这种电池的系统和方法。 在一个实施例中，提供了用于形成能量存储装置的阳极结构。 阳极结构包括柔性导电基板，形成在导电基板上的多个导电微结构，包括形成在多个柱状突起上的多个柱状突起和树突状结构以及形成在多个导电微结构上的多个锡颗粒。 在另一个实施方案中，阳极结构还包括锡成核层，其包含形成在柔性导电基底上的锡颗粒在柔性导电基底和多个导电微结构之间。

公开(公告)号：US20100216026A1

公开(公告)日：2010-08-26

申请号：US12459313

申请日：2009-06-30

申请人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Robert Z. Bachrach

发明人： Sergey D. Lopatin ,  Dmitri A. Brevnov ,  Robert Z. Bachrach

IPC分类号： H01M2/16 ,  C25D5/00

CPC分类号： H01M10/0585 ,  C25D1/00 ,  C25D1/006 ,  H01M2/1653 ,  H01M2/1686 ,  H01M4/0428 ,  H01M4/133 ,  H01M4/1393 ,  H01M4/364 ,  H01M4/587 ,  H01M4/667 ,  H01M4/70 ,  H01M6/40 ,  H01M10/0525 ,  H01M10/0565 ,  H01M10/0566 ,  H01M10/058

摘要： A method for forming a battery from via thin-film deposition processes is disclosed. A mesoporous carbon material is deposited onto a surface of a conductive substrate that has high surface area, conductive micro-structures formed thereon. A porous, dielectric separator layer is then deposited on the layer of mesoporous carbon material to form a half cell of an energy storage device. The mesoporous carbon material is made up of CVD-deposited carbon fullerene “onions” and carbon nano-tubes, and has a high porosity capable of retaining lithium ions in concentrations useful for storing significant quantities of electrical energy. Embodiments of the invention further provide for the formation of an electrode having a high surface area conductive region that is useful in a battery structure. In one configuration the electrode has a high surface area conductive region comprising a porous dendritic structure that can be formed by electroplating, physical vapor deposition, chemical vapor deposition, thermal spraying, and/or electroless plating techniques.

摘要翻译： 公开了一种通过薄膜沉积工艺形成电池的方法。 在其上形成有高表面积的导电微结构的导电性基板的表面上沉积介孔碳材料。 然后将多孔介电分离器层沉积在介孔碳材料层上以形成储能装置的半电池。 中孔碳材料由CVD沉积的碳富勒烯“洋葱”和碳纳米管组成，并且具有能够将锂离子保留在用于储存大量电能的浓度的高孔隙率。 本发明的实施例还提供了一种用于电池结构的具有高表面积导电区域的电极的形成。 在一种配置中，电极具有高的表面积导电区域，其包括通过电镀，物理气相沉积，化学气相沉积，热喷涂和/或化学镀技术形成的多孔树枝状结构。

公开(公告)号：US07226856B1

公开(公告)日：2007-06-05

申请号：US10990273

申请日：2004-11-15

申请人： Sergey D. Lopatin ,  Robert Fiordalice ,  Faivel Pintchovski ,  Igor Ivanov ,  Wen Z. Kong ,  Artur Kolics

发明人： Sergey D. Lopatin ,  Robert Fiordalice ,  Faivel Pintchovski ,  Igor Ivanov ,  Wen Z. Kong ,  Artur Kolics

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76868 ,  H01L21/76874 ,  Y10S977/723

摘要： An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is formed over the dielectric layer in the trench and via, and a conductor is deposited over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.

摘要翻译： 提供一种集成电路和集成电路的制造方法，包括提供具有在电介质层中设置的沟槽和通孔的集成电路。 纳米电极阵列形成在沟槽和通孔中的电介质层之上，导体沉积在纳米电极阵列上。 导体和纳米电极阵列与电介质层的表面共面。

公开(公告)号：US06861349B1

公开(公告)日：2005-03-01

申请号：US10145944

申请日：2002-05-15

申请人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

发明人： Sergey D. Lopatin ,  Paul R. Besser ,  Matthew S. Buynoski ,  Pin-Chin Connie Wang

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76874

摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.

摘要翻译： 一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金 元素进入阻挡材料层上的界面层，在界面层上沉积合金层。 植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

公开(公告)号：US06836398B1

公开(公告)日：2004-12-28

申请号：US10284769

申请日：2002-10-31

申请人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Minh Van Ngo ,  Mark S. Chang ,  Sergey D. Lopatin ,  Angela T. Hui ,  Christopher F. Lyons ,  Patrick K. Cheung ,  Ashok M. Khathuria

发明人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Minh Van Ngo ,  Mark S. Chang ,  Sergey D. Lopatin ,  Angela T. Hui ,  Christopher F. Lyons ,  Patrick K. Cheung ,  Ashok M. Khathuria

IPC分类号： H01G435

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L21/3212 ,  H01L27/285 ,  H01L28/75

摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.

摘要翻译： 本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。 本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。 在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。 还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。 因此，钝化层与用于形成电极的还原CMP工艺结合形成。

公开(公告)号：US06835655B1

公开(公告)日：2004-12-28

申请号：US09994397

申请日：2001-11-26

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

IPC分类号： H01L2144

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76859 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper layer to form a barrier material layer separating the via from the copper layer, implanting a metal species into the barrier material layer, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted metal species can make the barrier material layer more resistant to copper diffusion from the copper layer.

摘要翻译： 在集成电路制造工艺中注入铜阻挡材料以提高电性能的方法可以包括在集成电路基板上提供铜层，在位于铜层上方的通孔的底部和侧面提供阻挡材料以形成屏障 将所述通孔与所述铜层分离的材料层，将金属物质注入到所述阻挡材料层中，以及在所述通孔上方提供导电层，使得所述通孔将所述导电层电连接到所述铜层。 注入的金属物质可以使阻挡材料层更能抵抗铜层从铜层扩散。