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    Self-aligned borderless contacts for high density electronic and memory device integration
    11.
    发明授权
    Self-aligned borderless contacts for high density electronic and memory device integration 有权
    用于高密度电子和存储器件集成的自对准无边界触点

    公开(公告)号：US08754530B2

    公开(公告)日：2014-06-17

    申请号：US12193339

    申请日：2008-08-18

    申请人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    发明人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

    摘要翻译： 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION
    13.
    发明申请
    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION 有权
    用于高密度电子和存储器件集成的自对准无边界联系

    公开(公告)号：US20100038723A1

    公开(公告)日：2010-02-18

    申请号：US12193339

    申请日：2008-08-18

    申请人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    发明人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

    摘要翻译： 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

    Filling Narrow Openings Using Ion Beam Etch
    17.
    发明申请
    Filling Narrow Openings Using Ion Beam Etch 有权
    使用离子束蚀刻填充狭窄的开口

    公开(公告)号：US20120217590A1

    公开(公告)日：2012-08-30

    申请号：US13036113

    申请日：2011-02-28

    申请人： Katherina E. Babich ,  Alessandro C. Callegari ,  Christopher D. Sheraw ,  Eugene J. O'Sullivan

    发明人： Katherina E. Babich ,  Alessandro C. Callegari ,  Christopher D. Sheraw ,  Eugene J. O'Sullivan

    IPC分类号： H01L29/78 ,  H01L21/4763

    CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer.

    摘要翻译： 通常，本文公开的主题涉及现代复杂的半导体器件及其形成方法，其中可以使用多层金属填充物来填充形成在层间电介质层中的窄开口。 本文公开的一种说明性方法包括在半导体衬底上形成的半导体器件的电介质材料层中形成开口，该开口具有侧壁和底表面。 该方法还包括通过在开口内形成第一层并且至少在开口的侧壁和底表面上方形成在半导体器件上方形成第一填充材料层。 此外，该方法包括执行第一成角度蚀刻工艺，以通过至少部分地去除开口的入口附近的第一层的第一部分，而不去除第二层第二层第一填充材料的第二层 所述第一层的部分靠近所述开口的底部，并且通过在所述开口内部和所述第一层上方形成所述第二层，在所述半导体器件上方形成第二填充材料层。