公开(公告)号：US20210158867A1

公开(公告)日：2021-05-27

申请号：US17016765

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G06F11/10 ,  G06F3/06

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

公开(公告)号：US20210082497A1

公开(公告)日：2021-03-18

申请号：US17014293

申请日：2020-09-08

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06F3/06

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

公开(公告)号：US20230410899A1

公开(公告)日：2023-12-21

申请号：US18364524

申请日：2023-08-03

Applicant: KIOXIA CORPORATION

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C11/56 ,  G06F3/0604 ,  G06F3/0655 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06F3/0679

Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.

公开(公告)号：US20230253054A1

公开(公告)日：2023-08-10

申请号：US18134719

申请日：2023-04-14

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/32 ,  H10B69/00

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US20230253029A1

公开(公告)日：2023-08-10

申请号：US17842516

申请日：2022-06-16

Applicant: Kioxia Corporation

Inventor： Akiyuki MURAYAMA ,  Kikuko SUGIMAE ,  Katsuya NISHIYAMA ,  Yusuke ARAYASHIKI ,  Motohiko FUJIMATSU ,  Kyosuke SANO ,  Noboru SHIBATA

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/06

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/063

Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.

公开(公告)号：US20220366973A1

公开(公告)日：2022-11-17

申请号：US17874968

申请日：2022-07-27

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Yasuyuki MATSUDA

IPC: G11C11/56 ,  G11C11/408 ,  G11C16/08

Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

公开(公告)号：US20220084609A1

公开(公告)日：2022-03-17

申请号：US17201332

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Akiyuki MURAYAMA ,  Kikuko SUGIMAE ,  Katsuya NISHIYAMA ,  Motohiko FUJIMATSU ,  Noboru SHIBATA

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.

公开(公告)号：US20200211655A1

公开(公告)日：2020-07-02

申请号：US16724100

申请日：2019-12-20

Applicant: KIOXIA CORPORATION

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G06F3/06

Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

公开(公告)号：US20240339160A1

公开(公告)日：2024-10-10

申请号：US18746964

申请日：2024-06-18

Applicant: Kioxia Corporation

Inventor： Tokumasa HARA ,  Noboru SHIBATA

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/102 ,  G11C16/30 ,  G11C16/3404

Abstract: According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address.

公开(公告)号：US20240185930A1

公开(公告)日：2024-06-06

申请号：US18527941

申请日：2023-12-04

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA

IPC: G11C16/26 ,  G11C7/08 ,  G11C8/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/26 ,  G11C7/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  G11C2207/2245

Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.