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19 条记录 (耗时 0.028 秒)

    Semiconductor memory device
    11.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07085148B2

    公开(公告)日：2006-08-01

    申请号：US10937441

    申请日：2004-09-10

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Yasuo Murakuki

    IPC分类号： G11C7/06

    CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C11/22

    摘要： A semiconductor memory device having a semiconductor substrate includes a plurality of reference cells 4 and a plurality of bit lines 10. The reference cells 4 are formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines 10. The bit lines 10 form pairs each composed of two adjacent bit lines. Two bit lines 10 in each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lines 10 has at least one cross section 11 where one of the pair of bit lines 10 crosses the other, to switch between the first parallel state and the second parallel state. The cross section 11 is provided in the predetermined region of the semiconductor substrate such that the length of a bit line 10 in the first parallel state is equal to the length of the bit line 10 in the second parallel state. The semiconductor memory device is reduced in size.

    摘要翻译： 具有半导体衬底的半导体存储器件包括多个参考单元4和多个位线10。 参考单元4形成在半导体衬底的垂直于位线10的预定区域的中心线附近的区域中。 位线10形成每对由两个相邻位线组成的对。 每对中的两个位线10具有第一并联状态和第二并行状态，其中两个位线的位置与第一并行状态相反。 每对位线10具有至少一个横截面11，其中一对位线10中的一个与另一个位线交叉，以在第一并行状态和第二平行状态之间切换。 横截面11设置在半导体衬底的预定区域中，使得位于第一并联状态的位线10的长度等于位线10在第二平行状态下的长度。 半导体存储器件的尺寸减小。

    Semiconductor memory device
    13.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20060285378A1

    公开(公告)日：2006-12-21

    申请号：US11356213

    申请日：2006-02-17

    申请人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

    发明人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

    摘要翻译： 为了省略存储单元的存储节点和单元板极线之间的复位晶体管，单元板线固定为基本上等于接地电位的电位，并且用正和负电压驱动位线。

    Semiconductor device
    14.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06320229B1

    公开(公告)日：2001-11-20

    申请号：US09301354

    申请日：1999-04-29

    申请人： Toshitaka Uchikoba ,  Masahiko Sakagami ,  Akihiro Yamamoto

    发明人： Toshitaka Uchikoba ,  Masahiko Sakagami ,  Akihiro Yamamoto

    IPC分类号： H01L2974

    CPC分类号： H01L27/0288 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： In a semiconductor substrate of a first conductivity type, first and second high-concentration layers of a second conductivity type are formed in spaced relation to each other. A reference voltage is applied to the second high-concentration layer. A conductive layer provides an electrical connection between the first high-concentration layer and an input pad for inputting an input signal to an input circuit or input/output circuit. A first low-concentration layer of the second conductivity type is formed in the region of the semiconductor substrate immediately underlying the first high-concentration layer.

    摘要翻译： 在第一导电类型的半导体衬底中，第二导电类型的第一和第二高浓度层彼此间隔开地形成。 对第二高浓度层施加参考电压。 导电层在第一高浓度层和输入焊盘之间提供电连接，用于将输入信号输入到输入电路或输入/输出电路。 在第一高浓度层正下方的半导体衬底的区域中形成第二导电类型的第一低浓度层。

    Memory control device
    15.
    发明授权
    Memory control device 失效
    存储控制装置

    公开(公告)号：US5233557A

    公开(公告)日：1993-08-03

    申请号：US723613

    申请日：1991-07-01

    申请人： Masahiko Sakagami ,  Yoshikazu Maeyama

    发明人： Masahiko Sakagami ,  Yoshikazu Maeyama

    IPC分类号： G11C11/413 ,  G06F1/06 ,  G11C7/22

    CPC分类号： G11C7/22

    摘要： A memory control device for controlling a random access memory provides with an arbiter for generating write start and read start signals in response to WRITE and READ commands which are obtained by frequency-dividing writing and reading clock signals, respectively and a memory control circuit comprised of first and second delay circuits for delaying the write start and read start signals by predetermined times, respectively, and first and second RS flip-flop circuits for generating write and read control signals in response to the write start and read start signals, respectively, which are reset by reset signals output from the first and second delay circuits, respectively.

    Dynamic type semiconductor memory
    16.
    发明授权
    Dynamic type semiconductor memory 失效
    动态型半导体存储器

    公开(公告)号：US5227697A

    公开(公告)日：1993-07-13

    申请号：US618800

    申请日：1990-11-28

    申请人： Masahiko Sakagami

    发明人： Masahiko Sakagami

    IPC分类号： G11C7/20 ,  G11C11/4072

    CPC分类号： G11C7/20 ,  G11C11/4072

    摘要： A dynamic type semiconductor memory in which a bit line is made to be connected to an electric potential different from a precharge potential after a precharge of the bit line is effected and one of word lines is selected and before a sensing amplifier operates. Thereby, all data stored in memory cells of the same row address can be cleared or preset in a cycle. Further, data stored in all of memory cells of which the number is equal to that of row addresses multiplied by that of column addresses can be cleared or preset in cycles of which the number is equal to that of the row addresses. Consequently, a clearance of contents of or a presetting of all memory cells can be effected at a high speed.

    Arbiter circuit using plural-reset RS flip-flops
    18.
    发明授权
    Arbiter circuit using plural-reset RS flip-flops 失效
    ARBITER电路使用PLORAL-RESET RS FLIP-FLOPS

    公开(公告)号：US5065052A

    公开(公告)日：1991-11-12

    申请号：US538244

    申请日：1990-06-14

    申请人： Masahiko Sakagami ,  Hideki Kawai

    发明人： Masahiko Sakagami ,  Hideki Kawai

    IPC分类号： G11C11/407 ,  G06F13/16 ,  G06F13/364 ,  G11C11/401 ,  H03K17/00

    CPC分类号： G06F13/364 ,  G06F13/1605

    摘要： This invention is realized, in sum, by providing at least one reset input terminal, aside from a reset input terminal to which a request end signal is supplied, to output stage RS flip-flops of plural latch circuits to which plural request signals are supplied respectively. The signal of a first output terminal of the output stage RS flip-flop of a specified latch circuit of the plural latch circuits is supplied to a reset input terminal of the output stage RS flip-flop of the other latch circuit and a delay circuit is connected between a second output terminal and the other reset input terminal of the output stage RS flip-flops of each latch circuit. Accordingly, if plural request signals are supplied at substantially the same time, the competition of these request signals may be settled. Besides, by setting the delay time of each delay circuit longer than the time required from the supply of the signal to the set input terminal of the corresponding output stage RS flip-flop until the signal is latched in the output terminal, even if pulsive signals are supplied to the output stage RS flip-flops, oscillation of the output stage RS flip-flops may be prevented.

    Semiconductor integrated circuit device including shift register having substantially equalized wiring between stages thereof
    19.
    发明授权
    Semiconductor integrated circuit device including shift register having substantially equalized wiring between stages thereof 失效
    包括移位寄存器的半导体集成电路器件，其阶段之间布线基本相等

    公开(公告)号：US4821299A

    公开(公告)日：1989-04-11

    申请号：US15347

    申请日：1987-02-17

    申请人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Masahiko Sakagami

    发明人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Masahiko Sakagami

    IPC分类号： G11C19/00 ,  G11C19/18 ,  G11C19/28 ,  H03K23/54

    CPC分类号： G11C19/188

    摘要： In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

    摘要翻译： 在具有至少一个移位寄存器的半导体集成电路器件中，移位寄存器的多个5级串联电连接，所述移位寄存器的第1级位于与数据输入端最接近的位置， 阶段是以间隔顺序和直线定位的; 阶段的链条在特定阶段被折叠，并且进一步的后续阶段以间隔顺序和直线地定位，以便填充其他阶段之间的空间，因此，所述阶段之间的负载电容的不平衡和功能不平衡 移位寄存器之间可以最小化。