公开(公告)号：US20160049201A1

公开(公告)日：2016-02-18

申请号：US14668790

申请日：2015-03-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Kuo-Pin CHANG

IPC: G11C16/14

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C2216/18 ,  H01L27/11551 ,  H01L27/11578

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.

Abstract translation: 提供了一种用于操作包括多个存储单元块的NAND阵列的方法。 多个块中的存储单元块包括在第一串选择开关和第二串选择开关之间具有通道线的多个NAND串。 多个NAND串在第一和第二串选择开关之间共享一组字线。 通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。 字线侧擦除电压被施加到所选择的子集，包括由所选择的块中的NAND串共享的一组字线中的一个以上的成员，以在耦合到所选子集的存储器单元中诱发隧穿，同时在存储器单元中禁止隧道 耦合到包括该组字线的多于一个成员的未选择子集。

公开(公告)号：US20250107110A1

公开(公告)日：2025-03-27

申请号：US18471292

申请日：2023-09-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU ,  Cheng-Yu LEE

IPC: H10B99/00

Abstract: Provided is a capacitor structure for a three-dimensional AND flash memory device. The capacitor includes a substrate having a capacitor array region and a capacitor staircase region, a circuit under array (CuA) structure disposed on the substrate, a bottom conductive layer disposed on the CuA structure, a stacked structure disposed on the bottom conductive layer, and pillar structures. The stacked structure includes dielectric layers and conductive layers alternately stacked. The conductive layers in the capacitor staircase region are arranged in a staircase form. The pillar structures are arranged in an array in the capacitor array region and penetrate through the stacked structure and the bottom conductive layer. A part of the conductive layers is 10 electrically connected to a first common voltage source, and the rest of the conductive layers and the bottom conductive layer are electrically connected to a second common voltage source.

公开(公告)号：US20240407181A1

公开(公告)日：2024-12-05

申请号：US18457412

申请日：2023-08-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H10B99/00 ,  G11C5/06 ,  G11C11/39 ,  H01L29/74

Abstract: A memory device based on thyristors, comprises the following elements. A plurality of gate structures, are continuous structures in the first direction. A plurality of bit lines, extending in a second direction substantially perpendicular to the first direction. A plurality of source lines, extending in the first direction. A plurality of channels, extending in a third direction substantially perpendicular to the first direction and the second direction, and penetrating the gate structures. The first doped regions of the channels are coupled to the bit lines, and the second doped regions of the channels are coupled to the source lines. A plurality of memory units formed by the gate structures and corresponding channels. The source lines are arranged in sequence according to the second direction to form a stair structure, and the lengths of the source lines decrease in sequence in the first direction.

公开(公告)号：US20230240062A1

公开(公告)日：2023-07-27

申请号：US17746996

申请日：2022-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Sheng-Ting FAN ,  Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/108 ,  H01L23/528

CPC classification number: H01L27/10802 ,  H01L23/5283

Abstract: A memory structure includes a substrate; a first gate structure, a second gate structure and a third gate structure disposed on the substrate, separated from each other along the first direction and respectively extending along the second direction and the third direction; channel bodies separated from each other and passing through the first gate structure, the second gate structure and the third gate structure along the first direction; dielectric films disposed between the first gate structure, the second gate structure, the third gate structure and the channel bodies; and a first side plug electrically connected to the substrate and the channel bodies. The first gate structure, the second gate structure and the third gate structure surround each of the dielectric films and each of the channel bodies, and the dielectric films do not include a charge storage structure.

公开(公告)号：US20220375523A1

公开(公告)日：2022-11-24

申请号：US17325243

申请日：2021-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng LIN ,  Su-Chueh LO ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

公开(公告)号：US20220068922A1

公开(公告)日：2022-03-03

申请号：US17005550

申请日：2020-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/108 ,  H01L27/11556 ,  H01L27/11582 ,  G11C11/39 ,  G11C11/56

Abstract: A memory structure is provided. The memory structure includes a first channel body, a first source region, a first drain region, a first gate structure and a second gate structure. The first source region has a first conductivity and connects to a first end of the first channel body. The first drain region has a second conductivity and connects to a second end of the first channel body separated from the first end. The first gate structure is disposed adjacent to the first channel body and between the first end and the second end. The second gate structure disposed adjacent to the first channel body and between the first end and the second end.

公开(公告)号：US20210335804A1

公开(公告)日：2021-10-28

申请号：US16857226

申请日：2020-04-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a first staircase structure, a second staircase structure, a conductive pillar, and a contact pillar. The first staircase structure includes conductive stair layers. The conductive pillar passes through the second staircase structure. The conductive pillar has an upper conductive pillar end and a lower conductive pillar end opposing to the upper conductive pillar end. The contact pillar is electrically connected on one conductive stair layer of the conductive stair layers. The contact pillar has an upper contact end and a lower contact end opposing to the upper contact end. The upper contact end and the lower contact end are respectively electrically connected to the upper conductive pillar end of the conductive pillar and the one conductive stair layer.

公开(公告)号：US20170018570A1

公开(公告)日：2017-01-19

申请号：US15279203

申请日：2016-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Teng-Hao YEH

IPC: H01L27/115 ,  H01L27/02 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L28/90 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/60

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

Abstract translation: 集成电路包括具有导电条的堆叠的3D NAND存储器阵列和具有堆叠的电容器端子条的电容器。 导电带堆叠中的多个导电条和电容器端子条的堆叠的多个电容器端子条相对于基板共享相同的多个平面位置。 在相同多个平面位置中的不同平面位置表示电容器端子条的堆叠中的不同的电容器端子条和导电条的堆叠中的不同的导电条，以及表征导电条的堆叠中的导电条的同一平面位置 电容器端子排堆叠中的电容器端子条表示导电条和电容器端子条相对于彼此具有相同的垂直位置。

公开(公告)号：US20140362644A1

公开(公告)日：2014-12-11

申请号：US14209962

申请日：2014-03-13

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting LUE ,  Wei-Chen CHEN

IPC: G11C16/12 ,  G11C16/14 ,  H01L27/115 ,  G11C16/26

CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

Abstract: A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at cross points in the channel region. The bit line is coupled to a first end of the semiconductor strip, and a reference line is coupled to a second end of the semiconductor strip. Charge storage structures are disposed between the word lines in the plurality word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip between the bit line and the reference line. Biasing unselected word lines can be used to select n-channel or p-channel modes in a single selected cell for read, program or erase.

Abstract translation: 存储器结构包括具有多栅极沟道区的半导体条，与沟道区的第一侧相邻的p型端子区和与沟道区的第二侧相邻的n型端子区。 多个字线布置成在沟道区域的交叉点处穿过半导体条。 位线耦合到半导体条的第一端，并且参考线耦合到半导体条的第二端。 电荷存储结构设置在多个字线中的字线和半导体条的沟道区之间，由此存储单元沿着位线和参考线之间的半导体条串联设置。 可以使用偏移未选择的字线来选择单个所选单元格中的n沟道或p沟道模式进行读取，编程或擦除。

公开(公告)号：US20240242759A1

公开(公告)日：2024-07-18

申请号：US18319513

申请日：2023-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: G11C11/4097 ,  G11C11/4067 ,  H10B12/10

CPC classification number: G11C11/4097 ,  G11C11/4067 ,  H10B12/10

Abstract: A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.