公开(公告)号：US20160329243A1

公开(公告)日：2016-11-10

申请号：US14707648

申请日：2015-05-08

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/29 ,  H01L23/31 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/28247 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L31/1868 ,  H01L33/44

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 提供基板。 在基板上形成具有开口的材料层。 在开口的侧壁和衬底上形成第一钝化材料层。 对第一钝化材料层进行处理工艺以形成第二钝化材料层。 第二钝化材料层的第一表面和第二钝化材料层的第二表面（在内侧）的性质不同，并且第一表面位于第二钝化材料层的相对远离第二钝化材料层的一侧 材料层。

公开(公告)号：US20160204123A1

公开(公告)日：2016-07-14

申请号：US14596022

申请日：2015-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ta-Hone Yang ,  Shih-Ping Hong ,  Nan-Tsu Lian ,  Kuang-Chao Chen

IPC: H01L27/115 ,  H01L23/535 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L21/768 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/40117 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising providing a substrate and forming a plurality of layers over the substrate. The plurality of layers comprise alternating first composition material layers and second composition material layers. The method further comprises forming an elongated post. The post extends from at least the top surface of the substrate.

Abstract translation: 本示例实施例大体上涉及制造半导体器件的半导体器件和方法，包括提供衬底并在衬底上形成多个层。 多个层包括交替的第一组合物材料层和第二组合物材料层。 该方法还包括形成细长柱。 柱从至少衬底的顶表面延伸。

公开(公告)号：US20170053867A1

公开(公告)日：2017-02-23

申请号：US14827971

申请日：2015-08-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Yao-An Chung

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/48 ,  H01L23/528

CPC classification number: H01L23/5222 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract translation: 提供了包括多个第一导电线层，多个支撑结构和电荷存储层的存储器件。 每个第一导电线层沿着由第一方向和第二方向限定的平面延伸。 每个第一导线层包括沿着第一方向延伸的多个第一导电线。 支撑结构位于相邻的第一导线层之间。 电荷存储层覆盖第一导电线的上表面，下表面和两个侧表面以及支撑结构的表面。

公开(公告)号：US09559049B1

公开(公告)日：2017-01-31

申请号：US14827971

申请日：2015-08-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Yao-An Chung

IPC: H01L45/00 ,  H01L43/12 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/48

CPC classification number: H01L23/5222 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract translation: 提供了包括多个第一导电线层，多个支撑结构和电荷存储层的存储器件。 每个第一导电线层沿着由第一方向和第二方向限定的平面延伸。 每个第一导线层包括沿着第一方向延伸的多个第一导电线。 支撑结构位于相邻的第一导线层之间。 电荷存储层覆盖第一导电线的上表面，下表面和两个侧表面以及支撑结构的表面。

公开(公告)号：US20170011995A1

公开(公告)日：2017-01-12

申请号：US14795689

申请日：2015-07-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Shih-Ping Hong

IPC: H01L23/528 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11578

Abstract: Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.

Abstract translation: 提供了包括多个位线层和多个支撑结构的存储器件。 每个位线层在由第一方向和第二方向限定的平面中延伸，并且具有沿着第一方向延伸的多个位线。 每个位线具有交替布置的多个宽部分和多个窄部分。 支撑结构设置在相邻位线层的相应位线的宽部分之间。 此外，每个位线的每个窄部分的横截面基本上具有椭圆形形状，并且每个窄部分具有大于约30％的舍入率（RR）。

公开(公告)号：US09299667B2

公开(公告)日：2016-03-29

申请号：US14259771

申请日：2014-04-23

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Shih-Ping Hong ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L23/00 ,  H01L29/49

CPC classification number: H01L23/564 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract translation: 描述了一种促进集成电路的密集配置的阵列中的晶体管之间的层间电介质填充的方法。 公开了利用微加载效应以在晶体管之间产生T形轮廓的蚀刻工艺。 微载物对集成电路的外围区域中的晶体管具有可忽略的影响。