公开(公告)号：US20180277179A1

公开(公告)日：2018-09-27

申请号：US15818768

申请日：2017-11-21

Applicant: MEDIATEK INC.

Inventor： Chia-Wei Wang

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/06 ,  G11C7/12 ,  G11C8/18 ,  G06F17/50

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G06F17/5045 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/12 ,  G11C8/06 ,  G11C8/18

Abstract: An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.

公开(公告)号：US09690365B2

公开(公告)日：2017-06-27

申请号：US15138462

申请日：2016-04-26

Applicant: MediaTek Inc.

Inventor： Hugh Thomas Mair ,  Yi-Te Chiu ,  Che-Wei Wu ,  Lee-Kee Yong ,  Chia-Wei Wang ,  Cheng-Hsing Chien ,  Uming Ko

IPC: G11C7/22 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

公开(公告)号：US10541023B2

公开(公告)日：2020-01-21

申请号：US16019464

申请日：2018-06-26

Applicant: MEDIATEK INC.

Inventor： Chia-Wei Wang ,  Yi-Te Chiu ,  Wen-Pin Hsieh

IPC: G11C11/41 ,  G11C11/419 ,  G11C5/00

Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

公开(公告)号：US20190108890A1

公开(公告)日：2019-04-11

申请号：US16211524

申请日：2018-12-06

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/18 ,  G11C7/06

CPC classification number: G11C17/18 ,  G11C7/06 ,  G11C7/067

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US20190074054A1

公开(公告)日：2019-03-07

申请号：US16019464

申请日：2018-06-26

Applicant: MEDIATEK INC.

Inventor： Chia-Wei Wang ,  Yi-Te Chiu ,  Wen-Pin Hsieh

IPC: G11C11/419

Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

公开(公告)号：US20180114583A1

公开(公告)日：2018-04-26

申请号：US15492014

申请日：2017-04-20

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C7/06 ,  G11C7/067

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US09640229B2

公开(公告)日：2017-05-02

申请号：US14692057

申请日：2015-04-21

Applicant: MediaTek Inc.

Inventor： Dao-Ping Wang ,  Chia-Wei Wang

IPC: G11C5/06 ,  G11C7/06 ,  G11C7/00 ,  G11C16/12 ,  G11C17/12 ,  G11C17/14 ,  G11C11/56 ,  G11C5/14

CPC classification number: G11C7/06 ,  G11C5/06 ,  G11C5/063 ,  G11C5/14 ,  G11C7/00 ,  G11C11/5692 ,  G11C16/12 ,  G11C17/12 ,  G11C17/14

Abstract: A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.

公开(公告)号：US09269405B1

公开(公告)日：2016-02-23

申请号：US14533065

申请日：2014-11-04

Applicant: MEDIATEK INC.

Inventor： Chia-Wei Wang

IPC: G11C17/00 ,  G11C5/06 ,  G11C7/06

CPC classification number: G11C17/12 ,  G11C17/123 ,  G11C17/126 ,  H01L27/11226

Abstract: A semiconductor memory includes: a first switching transistor, wherein the first switching transistor has a first terminal, a second terminal, and a third terminal, and the second terminal is coupled to a first word-line; a first differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the first terminal of the first switching transistor for storing first information; and a second differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the third terminal of the first switching transistor for storing second information.

Abstract translation: 半导体存储器包括：第一开关晶体管，其中所述第一开关晶体管具有第一端子，第二端子和第三端子，并且所述第二端子耦合到第一字线; 具有非反相位线和反相位线的第一差分位线对，其中非反相位线及其反相位线互斥地耦合到第一开关的第一端子 用于存储第一信息的晶体管; 以及具有非反相位线和反相位线的第二差分位线对，其中非反相位线及其反相位线互相独立地耦合到第一 用于存储第二信息的开关晶体管。

公开(公告)号：US08824237B2

公开(公告)日：2014-09-02

申请号：US13835908

申请日：2013-03-15

Applicant: MediaTek Inc.

Inventor： Chia-Wei Wang

IPC: G11C8/00 ,  G11C8/10

CPC classification number: G11C8/10 ,  G11C5/14 ,  G11C8/08

Abstract: A pre-decoder for providing a pulse signal to a dual power rail word line driver is provided. The pre-decoder includes a clock generator, an address latch and decoder, a level shifter and a processing unit. The clock generator generates a first signal according to a clock, wherein the first signal is powered by a first supply voltage. The address latch and decoder decodes an address to obtain a second signal according to the first signal. The level shifter generates a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage. The processing unit generates the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage.

Abstract translation: 提供了一种用于向双电源轨线字线驱动器提供脉冲信号的预解码器。 预解码器包括时钟发生器，地址锁存器和解码器，电平转换器和处理单元。 时钟发生器根据时钟生成第一信号，其中第一信号由第一电源电压供电。 地址锁存器和解码器根据第一信号解码地址以获得第二信号。 电平移位器根据第一信号产生第三信号，其中第三信号由高于第一电源电压的第二电源电压供电。 处理单元根据第二信号和第三信号生成脉冲信号，其中脉冲信号由第二电源电压供电。