中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.018 seconds)

    Transistor and methods of forming transistors
    13.
    发明授权
    Transistor and methods of forming transistors 有权

    公开(公告)号：US10923593B1

    公开(公告)日：2021-02-16

    申请号：US16536479

    申请日：2019-08-09

    Applicant: Micron Technology, Inc.

    Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Darwin Franseda Fan ,  Ali Moballegh

    IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04

    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.

    SEMICONDUCTOR STRUCTURE FORMATION
    14.
    发明申请
    SEMICONDUCTOR STRUCTURE FORMATION 审中-公开

    公开(公告)号：US20200243528A1

    公开(公告)日：2020-07-30

    申请号：US16258987

    申请日：2019-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Devesh Dadhich Shreeram ,  Sanjeev Sapra ,  Masihhur R. Laskar ,  Darwin Franseda Fan ,  Jerome A. Imonigie

    IPC: H01L27/108

    Abstract: Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient B SPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.

    Devices and methods including an etch stop protection material
    15.
    发明授权
    Devices and methods including an etch stop protection material 有权

    公开(公告)号：US10573721B2

    公开(公告)日：2020-02-25

    申请号：US15470617

    申请日：2017-03-27

    Applicant: Micron Technology, Inc.

    Inventor： John Hopkins ,  Darwin Franseda Fan

    IPC: H01L29/49 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

    Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

    SINGLE-CRYSTAL TRANSISTORS FOR MEMORY DEVICES
    18.
    发明申请
    SINGLE-CRYSTAL TRANSISTORS FOR MEMORY DEVICES 有权

    公开(公告)号：US20250142909A1

    公开(公告)日：2025-05-01

    申请号：US19008075

    申请日：2025-01-02

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

    IPC: H10D62/40 ,  H10B12/00 ,  H10B53/30 ,  H10D62/17

    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

    Single-crystal transistors for memory devices
    19.
    发明授权
    Single-crystal transistors for memory devices 有权

    公开(公告)号：US12224310B2

    公开(公告)日：2025-02-11

    申请号：US18531525

    申请日：2023-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

    IPC: H01L29/10 ,  H01L29/04 ,  H10B12/00 ,  H10B53/30

    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

Patent Agency Ranking