公开(公告)号：US10438839B2

公开(公告)日：2019-10-08

申请号：US15687499

申请日：2017-08-27

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/764 ,  H01L21/20 ,  H01L21/02

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US20190019948A1

公开(公告)日：2019-01-17

申请号：US16125235

申请日：2018-09-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David H. Wells

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.

公开(公告)号：US10014211B2

公开(公告)日：2018-07-03

申请号：US15684722

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/20 ,  H01L21/764 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US09786548B2

公开(公告)日：2017-10-10

申请号：US14712219

申请日：2015-05-14

Applicant: Micron Technology, Inc.

Inventor： David H. Wells

IPC: H01L21/336 ,  H01L21/764 ,  H01L21/20 ,  H01L21/02

CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US09773734B2

公开(公告)日：2017-09-26

申请号：US15150734

申请日：2016-05-10

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Gurtej S. Sandhu

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/306 ,  H01L21/223 ,  H01L29/04 ,  H01L29/167 ,  H01L21/768 ,  H01L21/761 ,  H01L29/06 ,  H01L21/84 ,  H01L27/102 ,  H01L45/00 ,  H01L27/12 ,  H01L27/24 ,  H01L21/74

CPC classification number: H01L23/528 ,  H01L21/2236 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/84 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53271 ,  H01L27/1027 ,  H01L27/1203 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/06 ,  H01L29/167 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

公开(公告)号：US20170179383A1

公开(公告)日：2017-06-22

申请号：US15437308

申请日：2017-02-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David H. Wells

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/122 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/06

Abstract: A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.

公开(公告)号：US09425390B2

公开(公告)日：2016-08-23

申请号：US14515998

申请日：2014-10-16

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Christopher D. Cardon ,  Caner Onal

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L27/2427 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/33 ,  G11C2213/35 ,  G11C2213/52 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1608

Abstract: The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.

Abstract translation: 本公开包括使用用于存储器单元应用的选择装置的选择装置和方法。 示例性选择装置包括具有特定几何形状的第一电极，形成在第一电极上的半导体材料和形成在半导体材料上的具有特定几何形状的第二电极，其中所述选择装置被配置为响应于 施加到选择设备的信号。

公开(公告)号：US09355897B2

公开(公告)日：2016-05-31

申请号：US14607921

申请日：2015-01-28

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Gurtej S. Sandhu

IPC: H01L21/768 ,  H01L21/06 ,  H01L21/761 ,  H01L27/12 ,  H01L45/00 ,  H01L21/84 ,  H01L27/24 ,  H01L21/74 ,  H01L27/102 ,  H01L29/06

CPC classification number: H01L23/528 ,  H01L21/2236 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/84 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53271 ,  H01L27/1027 ,  H01L27/1203 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/06 ,  H01L29/167 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

Abstract translation: 公开了包括设置在介电材料的轨道之间的半导体材料的主体的半导体结构的形成方法。 这种方法可以包括用介电材料填充衬底中的多个沟槽，并且去除介电材料之间的衬底的部分以形成多个开口。 在一些实施例中，衬底的部分可以被底切以在主体下面形成连续的空隙，并且连续的空隙可以用导电材料填充。 在其他实施例中，暴露在开口内的基板的部分可以转化为硅化物材料，以在主体下面形成导电材料。 例如，导电材料可以用作导电线以电连接存储器件部件。 还公开了通过这些方法形成的半导体结构和器件。

公开(公告)号：US09006859B2

公开(公告)日：2015-04-14

申请号：US14034014

申请日：2013-09-23

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Gurtej S. Sandhu

IPC: H01L29/06 ,  H01L23/535 ,  H01L21/84 ,  H01L21/74 ,  H01L45/00 ,  H01L27/102 ,  H01L27/12 ,  H01L27/24 ,  H01L21/761

CPC classification number: H01L23/528 ,  H01L21/2236 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/743 ,  H01L21/761 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/84 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53271 ,  H01L27/1027 ,  H01L27/1203 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/06 ,  H01L29/167 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.

Abstract translation: 公开了形成半导体结构的方法，该半导体结构包括设置在电介质材料的轨道之间的半导体材料的主体。 这样的方法可以包括用电介质材料填充衬底中的多个沟槽并且去除介电材料之间的衬底的部分以形成多个开口。 在一些实施例中，衬底的部分可以被底切以在主体下面形成连续的空隙，并且连续的空隙可以用导电材料填充。 在其他实施例中，暴露在开口内的基板的部分可以转化为硅化物材料，以在主体下面形成导电材料。 例如，导电材料可以用作导电线以电连接存储器件部件。 还公开了通过这些方法形成的半导体结构和器件。

公开(公告)号：US08962431B2

公开(公告)日：2015-02-24

申请号：US14157192

申请日：2014-01-16

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  John Mark Meldrim ,  Rita J. Klein

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/283

CPC classification number: H01L21/28097 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32134 ,  H01L21/32139

Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.

Abstract translation: 一种形成含金属硅化物的材料的方法包括形成衬底，该衬底包括具有超过硅的第一金属上的第二金属的第一堆叠和在硅上的第二金属的第二叠层。 第一和第二种金属具有不同的组成。 基板经受使第二金属与第二堆叠中的硅反应以形成来自第二堆叠的含金属硅化物的材料的条件。 第一堆叠中的第二金属和硅之间的第一金属阻止从第一堆叠形成包括第二金属和硅的硅化物。 在形成含金属硅化物的材料之后，对第一金属，第二金属和含金属硅化物的材料进行蚀刻化学，从而选择性地相对于金属硅化物从衬底中蚀刻至少一些剩余的第一和第二金属 令人惊奇的材料。