公开(公告)号：US11694760B2

公开(公告)日：2023-07-04

申请号：US17382926

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulachet Tanpairoj ,  John Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/00

CPC classification number: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/886

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US20230205690A1

公开(公告)日：2023-06-29

申请号：US17646253

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He ,  Min Rui Ma

IPC: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

CPC classification number: G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/0483 ,  G06F2212/1032

Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.

公开(公告)号：US11550711B2

公开(公告)日：2023-01-10

申请号：US16565066

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

公开(公告)号：US20220300208A1

公开(公告)日：2022-09-22

申请号：US17631201

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Jingyuan Miao ,  Bin Zhao

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory read performance techniques are described. A memory system may receive a sequence of read commands. Based on detecting a set of consecutive read commands, the memory system may pre-read data from a second logical block address (LBA) in a non-volatile memory device to a volatile memory device based on receiving a first read command that includes a first LBA, where the second LBA is consecutive with the first LBA. The memory system may subsequently receive a second read command that includes the second LBA, and read out the second data without performing an additional access operation of the non-volatile storage device. In some examples, using such a pre-read, the memory system may capable of returning data in a different order than the order in which the commands were received.

公开(公告)号：US20220300179A1

公开(公告)日：2022-09-22

申请号：US17648399

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3296

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

公开(公告)号：US20220254434A1

公开(公告)日：2022-08-11

申请号：US17574024

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Chun S. Yeung ,  Deping He ,  Jonathan S. Parry

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/04

Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

公开(公告)号：US20220199190A1

公开(公告)日：2022-06-23

申请号：US17125503

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Deping He ,  Giuseppe Cariello

IPC: G11C29/50 ,  G11C5/14 ,  G11C29/56

Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

公开(公告)号：US20220179572A1

公开(公告)日：2022-06-09

申请号：US17682778

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He

IPC: G06F3/06 ,  G06F9/4401 ,  G06F11/10 ,  G11C29/52

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

公开(公告)号：US11314427B2

公开(公告)日：2022-04-26

申请号：US17000015

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US20220108753A1

公开(公告)日：2022-04-07

申请号：US17502497

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jingyuan Miao

IPC: G11C16/26 ,  G11C11/56

Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.