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11.发明公开公开(公告)号：US20240319886A1
公开(公告)日：2024-09-26
申请号：US18421893
申请日：2024-01-24
Applicant: Micron Technology, Inc.
Inventor： Peng Zhang , Lei Lin , Hanping Chen , Li-Te Chang , Zhengang Chen , Murong Lang , Zhenming Zhou
IPC: G06F3/06
CPC classification number: G06F3/0614 , G06F3/0652 , G06F3/0679
Abstract: A method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. The method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.
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公开(公告)号：US12009027B2
公开(公告)日：2024-06-11
申请号：US17561340
申请日：2021-12-23
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou
CPC classification number: G11C13/0033 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C11/5678
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.
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公开(公告)号：US20240021264A1
公开(公告)日：2024-01-18
申请号：US17812612
申请日：2022-07-14
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou , Ting Luo
CPC classification number: G11C29/52 , G11C29/50004 , G11C29/783
Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
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公开(公告)号：US20240331777A1
公开(公告)日：2024-10-03
申请号：US18615051
申请日：2024-03-25
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Charles S. Kwong , Murong Lang , Zhenming Zhou
CPC classification number: G11C16/26 , G06N20/00 , G11C16/0483
Abstract: Various embodiments use a cascade model to determine (e.g., predict or estimate) one or more read level voltage offsets used to read data from one or more memory cells of a memory device, which can be part of a memory sub-system.
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公开(公告)号：US20240329852A1
公开(公告)日：2024-10-03
申请号：US18739982
申请日：2024-06-11
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
Abstract: A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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Patent Agency Ranking
公开(公告)号：US20240321350A1
公开(公告)日：2024-09-26
申请号：US18734724
申请日：2024-06-05
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou
CPC classification number: G11C13/0033 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C11/5678
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zero-to-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.
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公开(公告)号：US20240311311A1
公开(公告)日：2024-09-19
申请号：US18672640
申请日：2024-05-23
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou
CPC classification number: G06F12/1027 , G06F12/0692 , G11C16/10 , G11C16/26 , G11C16/349 , G06F2212/68 , G11C16/0483
Abstract: A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. A read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.
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公开(公告)号：US12050777B2
公开(公告)日：2024-07-30
申请号：US17880213
申请日：2022-08-03
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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公开(公告)号：US20240071553A1
公开(公告)日：2024-02-29
申请号：US17894528
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Yu-Chung Lien , Murong Lang , Zhenming Zhou , Michael G. Miller
CPC classification number: G11C29/52 , G11C16/08 , G11C16/102 , G11C16/3404
Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.
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公开(公告)号：US20230207003A1
公开(公告)日：2023-06-29
申请号：US17561340
申请日：2021-12-23
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou
IPC: G11C13/00
CPC classification number: G11C13/0033 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C11/5678
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a cross-point memory array includes memory cells. A media controller reads one or more first memory cells and determines a read status. The read status indicates an error when reading the first memory cells. In response to this error, the controller refreshes the first memory cells. The controller uses the read status to determine zeroto-one failures associated with the first memory cells. If a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. The physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.
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