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    MEMORY KINK CHECKING
    11.
    发明申请
    MEMORY KINK CHECKING 有权
    内存闪烁检查

    公开(公告)号：US20140286092A1

    公开(公告)日：2014-09-25

    申请号：US14227295

    申请日：2014-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Uday Chandrasekhar ,  Mark A. Helm

    IPC: G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/3427 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454

    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

    Abstract translation: 本公开涉及内存扭结检查。 一个实施例包括根据第一存储器单元的编程状态来选择性地将多个电压中的一个施加到第一数据线，其中第一存储器单元耦合到第一数据线和所选择的存取线。 至少部分地由于施加到第一数据线的电压和至少第一数据线与第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到 第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到所选择的存取线。 响应于所确定的效果，在施加到第二存储器单元的后续编程脉冲期间，将扭结校正应用于第二数据线。

    Memory kink checking
    12.
    发明授权
    Memory kink checking 有权
    内存扭结检查

    公开(公告)号：US08804419B2

    公开(公告)日：2014-08-12

    申请号：US13938078

    申请日：2013-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Uday Chandrasekhar ,  Mark A. Helm

    IPC: G11C11/34

    CPC classification number: G11C16/3427 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454

    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

    Abstract translation: 本公开涉及内存扭结检查。 一个实施例包括根据第一存储器单元的编程状态来选择性地将多个电压中的一个施加到第一数据线，其中第一存储器单元耦合到第一数据线和所选择的存取线。 至少部分地由于施加到第一数据线的电压和至少第一数据线和第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到 第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到所选择的存取线。 响应于所确定的效果，在施加到第二存储器单元的后续编程脉冲期间，将扭结校正应用于第二数据线。

    METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING
    13.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING 有权
    用于数据传感的方法，设备和系统

    公开(公告)号：US20140189465A1

    公开(公告)日：2014-07-03

    申请号：US14109375

    申请日：2013-12-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Mark A. Helm ,  Uday Chandrasekhar

    IPC: G11C16/28 ,  G06F11/10 ,  H03M13/05

    CPC classification number: G11C16/28 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G11C16/3454 ,  G11C29/52 ,  H03M13/03 ,  H03M13/05

    Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

    Abstract translation: 本公开包括用于数据感测的方法和装置。 一种这样的方法包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测操作的数量的连续感测操作之间改变状态的数量存储器单元的数量，以及确定 至少部分地基于确定在连续感测操作之间改变状态的存储器单元的数量的确定数量，是否输出对应于多个连续感测操作中的一个的硬数据。

    MEMORY KINK CHECKING
    14.
    发明申请
    MEMORY KINK CHECKING 有权
    内存闪烁检查

    公开(公告)号：US20130294156A1

    公开(公告)日：2013-11-07

    申请号：US13938078

    申请日：2013-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Uday Chandrasekhar ,  Mark A. Helm

    IPC: G11C16/34

    CPC classification number: G11C16/3427 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3454

    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.

    Abstract translation: 本公开涉及内存扭结检查。 一个实施例包括根据第一存储器单元的编程状态来选择性地将多个电压中的一个施加到第一数据线，其中第一存储器单元耦合到第一数据线和所选择的存取线。 至少部分地由于施加到第一数据线的电压和至少第一数据线和第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到 第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到所选择的存取线。 响应于所确定的效果，在施加到第二存储器单元的后续编程脉冲期间，将扭结校正应用于第二数据线。

    STATUS CHECK USING CHIP ENABLE PIN
    15.
    发明申请
    STATUS CHECK USING CHIP ENABLE PIN 有权

    公开(公告)号：US20250094364A1

    公开(公告)日：2025-03-20

    申请号：US18967215

    申请日：2024-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

    IPC: G06F13/16 ,  G06F1/26

    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

    Status check using chip enable pin
    16.
    发明授权
    Status check using chip enable pin 有权

    公开(公告)号：US12169461B2

    公开(公告)日：2024-12-17

    申请号：US17963773

    申请日：2022-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

    IPC: G06F13/14 ,  G06F1/26 ,  G06F13/16

    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

    MULTI-LAYER CODE RATE ARCHITECTURE FOR COPYBACK BETWEEN PARTITIONS WITH DIFFERENT CODE RATES
    19.
    发明公开
    MULTI-LAYER CODE RATE ARCHITECTURE FOR COPYBACK BETWEEN PARTITIONS WITH DIFFERENT CODE RATES 审中-公开

    公开(公告)号：US20230297470A1

    公开(公告)日：2023-09-21

    申请号：US17696245

    申请日：2022-03-16

    Applicant: Micron Technology, Inc.

    Inventor： Mustafa N. Kaynak ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Mark A. Helm

    IPC: G06F11/10 ,  H03M13/29

    CPC classification number: G06F11/1068 ,  H03M13/2906

    Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

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