公开(公告)号：US10379738B2

公开(公告)日：2019-08-13

申请号：US15854622

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C13/00 ,  G11C16/04

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20190147963A1

公开(公告)日：2019-05-16

申请号：US16246009

申请日：2019-01-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/32

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US20190123058A1

公开(公告)日：2019-04-25

申请号：US16228574

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11526 ,  H01L27/11575 ,  G11C16/26 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11526 ,  G11C8/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.

公开(公告)号：US10210940B2

公开(公告)日：2019-02-19

申请号：US15685909

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US10170193B2

公开(公告)日：2019-01-01

申请号：US15935126

申请日：2018-03-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/16

Abstract: Methods of operating a memory, and apparatus so configured, include applying a first voltage level to a first voltage node connected to a first end of a string of series-connected memory cells, applying a second voltage level to a second voltage node connected to a second end of the string, applying a third voltage level less than the first and second voltage levels to a control gate of a first memory cell of the string while applying the first and second voltage levels to the first and second voltage nodes, and applying a fourth voltage level less than the third voltage level to a control gate of a second memory cell of the string while applying the third voltage level to the control gate of the first memory cell, wherein the first memory cell is closer to the first voltage node than the second memory cell.

公开(公告)号：US10109325B2

公开(公告)日：2018-10-23

申请号：US15878121

申请日：2018-01-23

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11529 ,  G11C16/26 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22 ,  G11C16/16 ,  G11C16/08 ,  G11C16/04

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US10096696B2

公开(公告)日：2018-10-09

申请号：US14294266

申请日：2014-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: H01L27/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112

Abstract: An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

公开(公告)号：US20180286484A1

公开(公告)日：2018-10-04

申请号：US15995626

申请日：2018-06-01

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  G11C16/04 ,  G11C8/10 ,  G11C5/02

CPC classification number: G11C16/08 ,  G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C16/0483

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

公开(公告)号：US10079064B2

公开(公告)日：2018-09-18

申请号：US15627212

申请日：2017-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C7/02

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

公开(公告)号：US20180254282A1

公开(公告)日：2018-09-06

申请号：US15450638

申请日：2017-03-06

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11526 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11573

CPC classification number: H01L27/11526 ,  G11C8/12 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.