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    Non-volatile memory device having configurable page size
    12.
    发明授权
    Non-volatile memory device having configurable page size 有权
    具有可配置页面大小的非易失性存储器件

    公开(公告)号：US09117527B2

    公开(公告)日：2015-08-25

    申请号：US14158116

    申请日：2014-01-17

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： Jin-Ki Kim

    IPC: G11C16/04 ,  G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10

    CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

    Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

    Abstract translation: 具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。 每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。 通过选择性地调整存储体的页面大小，相应地调整块大小。

    NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
    14.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES 有权
    具有多个外部电源的非易失性半导体存储器

    公开(公告)号：US20140104954A1

    公开(公告)日：2014-04-17

    申请号：US14107735

    申请日：2013-12-16

    Applicant: Mosaid Technologies Incorporated

    Inventor： Jin-Ki Kim ,  Peter Gillingham

    IPC: G11C16/30

    CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

    Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

    Abstract translation: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外，存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

    SYSTEM INCLUDING A PLURALITY OF ENCAPSULATED SEMICONDUCTOR CHIPS
    16.
    发明申请
    SYSTEM INCLUDING A PLURALITY OF ENCAPSULATED SEMICONDUCTOR CHIPS 有权
    包括多个封装的半导体晶体管的系统

    公开(公告)号：US20130271910A1

    公开(公告)日：2013-10-17

    申请号：US13917728

    申请日：2013-06-14

    Applicant: MOSAID Technologies Incorporated

    Inventor： Jin-Ki Kim

    IPC: G06F1/16

    CPC classification number: G06F1/16 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/049 ,  H01L2224/45099 ,  H01L2924/00

    Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

    Abstract translation: 公开了一种固态驱动器。 固态驱动器包括具有相对的第一和第二表面的电路板。 多个半导体芯片附接到固态驱动器的电路板的第一表面，并且固态驱动器的多个半导体芯片包括至少基本上封装在树脂中的至少一个存储器芯片。 还公开了一种在线存储器模块型形状电路板。 在线存储器模块型外形电路板具有相对的第一和第二表面。 多个半导体芯片附接到直列式存储模块型形状电路板的第一表面，并且这些半导体芯片包括至少基本上封装在树脂中的至少一个存储芯片。

    PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE
    17.
    发明申请
    PHASE-CHANGE MEMORY WITH MULTIPLE POLARITY BITS HAVING ENHANCED ENDURANCE AND ERROR TOLERANCE 有权
    具有增强耐久性和错误容忍度的多个极性位的相变记忆

    公开(公告)号：US20130215677A1

    公开(公告)日：2013-08-22

    申请号：US13860724

    申请日：2013-04-11

    Applicant: Mosaid Technologies Incorporated

    Inventor： Jin-Ki Kim ,  Peter B. Gillingham ,  William F. Petrie

    IPC: G11C13/00

    CPC classification number: G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C2029/0411 ,  G11C2211/5647

    Abstract: A Phase-Change Memory (PCM) apparatus including a data field for storing a data bits representing a data value or an inversion of the data value and a polarity field for storing a plurality of polarity bits for indicating that the data bits stored in the data field represent the data value or the inversion of the data value. In one embodiment an odd number of set polarity bits indicates that the data bits represent the inversion of the data value and an even number of set polarity bits indicates that the data bits represent the data value. The PCM apparatus has enhanced endurance and improved error tolerance.

    Abstract translation: 一种相变存储器（PCM）装置，包括用于存储表示数据值的数据位或数据值反转的数据位的数据场，以及用于存储用于指示存储在数据中的数据位的多个极性位的极性场 字段表示数据值或数据值的反转。 在一个实施例中，奇数个设置极性位指示数据位表示数据值的反转，偶数个设置的极性位表示数据位表示数据值。 PCM装置具有增强的耐久性和改进的误差容限。

    System including a plurality of encapsulated semiconductor chips
    18.
    发明授权
    System including a plurality of encapsulated semiconductor chips 有权
    系统包括多个封装的半导体芯片

    公开(公告)号：US08908378B2

    公开(公告)日：2014-12-09

    申请号：US13917728

    申请日：2013-06-14

    Applicant: MOSAID Technologies Incorporated

    Inventor： Jin-Ki Kim

    IPC: H05K1/14 ,  G06F3/06 ,  G06F1/16 ,  H05K3/28

    CPC classification number: G06F1/16 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K3/284 ,  H05K2201/10159 ,  H05K2203/049 ,  H01L2224/45099 ,  H01L2924/00

    Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

    Abstract translation: 公开了一种固态驱动器。 固态驱动器包括具有相对的第一和第二表面的电路板。 多个半导体芯片附接到固态驱动器的电路板的第一表面，并且固态驱动器的多个半导体芯片包括至少基本上封装在树脂中的至少一个存储器芯片。 还公开了一种在线存储器模块型形状电路板。 在线存储器模块型外形电路板具有相对的第一和第二表面。 多个半导体芯片附接到直列式存储模块型形状电路板的第一表面，并且这些半导体芯片包括至少基本上封装在树脂中的至少一个存储芯片。

    Dual function compatible non-volatile memory device
    19.
    发明授权
    Dual function compatible non-volatile memory device 有权
    双功能兼容的非易失性存储设备

    公开(公告)号：US08837237B2

    公开(公告)日：2014-09-16

    申请号：US14026359

    申请日：2013-09-13

    Applicant: MOSAID Technologies Incorporated

    Inventor： Jin-Ki Kim

    IPC: G11C7/00 ,  G11C16/20 ,  G11C5/14 ,  G11C16/06 ,  G11C7/20

    CPC classification number: G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

    Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

    Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

    Flash multi-level threshold distribution scheme
    20.
    发明授权
    Flash multi-level threshold distribution scheme 有权
    闪存多级阈值分配方案

    公开(公告)号：US08711621B2

    公开(公告)日：2014-04-29

    申请号：US13892743

    申请日：2013-05-13

    Applicant: MOSAID Technologies Incorporated

    Inventor： Jin-Ki Kim

    IPC: G11C11/34

    CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

    Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

    Abstract translation: 用于多电平闪存单元的阈值电压分配方案，其中擦除阈值电压和至少一个编程的阈值电压位于擦除电压域中。 在擦除电压域中至少有一个编程的阈值电压降低了Vread电压电平，以最小化读取干扰效应，同时随着编程状态之间的阈值电压距离最大化，延长多电平闪存单元的使用寿命。 编程电压域大于0V时，擦除电压域可以小于0V。 因此，用于程序验证和读取具有在擦除电压域中的编程阈值电压和编程电压域的多电平闪存单元的电路使用负和正高电压。

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