公开(公告)号：US09184096B2

公开(公告)日：2015-11-10

申请号：US13798275

申请日：2013-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee ,  Erh-Kun Lai

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/115

CPC classification number: H01L21/823878 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The method includes following steps. A first gate structure is formed on a substrate in a first region. A protecting layer is formed covering the first gate structure. A second gate structure is formed on the substrate in second region exposed by the protecting layer and adjacent to the first region.

Abstract translation: 提供了一种半导体结构及其制造方法。 该方法包括以下步骤。 第一栅极结构形成在第一区域中的衬底上。 形成覆盖第一栅极结构的保护层。 第二栅极结构形成在由保护层露出并邻近第一区域的第二区域中的衬底上。

公开(公告)号：US20150187694A1

公开(公告)日：2015-07-02

申请号：US14143040

申请日：2013-12-30

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  Yen-Hao Shih

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/105 ,  H01L21/3205 ,  H01L23/532

CPC classification number: H01L21/32133 ,  H01L21/32055 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括基板，堆叠结构，电介质层，导电结构，电介质结构和导电插塞。 堆叠结构包括交替布置的介电膜和导电膜。 介电层位于导电结构和层叠结构的侧壁之间。 电介质结构在堆叠结构上并且限定通孔。 导电插塞填充通孔并物理地接触由通孔暴露并与电介质层相邻的导电膜之一。

公开(公告)号：US09019768B1

公开(公告)日：2015-04-28

申请号：US14062487

申请日：2013-10-24

Applicant: Macronix International Co., Ltd.

Inventor： Guan-Ru Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C5/06 ,  H01L27/115 ,  G11C11/56

CPC classification number: H01L27/115 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage, depending on the memory cell selected for read. The same active strip stack selection structure can act as a pair of side gates for opposite sides of a first active strip stack, and as one side gate for each of the adjacent active strip stacks. Each active strip stack can have: a first structure from a first set acting as first and second side gates on a first side of word lines; and a second structure and a third structure from a second set respectively acting as third and fourth side gates on the second side of word lines.

Abstract translation: 半导体器件包括活性条。 活动带堆叠选择结构在第一和第二端之间的位置处电耦合到有源带堆叠，并且选择用于操作的特定的有源带堆叠。 在一个实施例中，取决于被选择用于读取的存储器单元，耦合到相对焊盘的不同焊盘具有更高的电压。 相同的有源带堆叠选择结构可以用作第一有源带堆叠的相对侧的一对侧栅极，以及用于每个相邻有源带堆叠的一个侧栅极。 每个有源条带堆叠可以具有：来自作为第一和第二侧栅极的第一集合的第一结构，位于字线的第一侧上; 以及分别充当字线第二侧上的第三和第四侧栅极的第二组的第二结构和第三结构。

公开(公告)号：US12200935B2

公开(公告)日：2025-01-14

申请号：US17684271

申请日：2022-03-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Ru Lee

IPC: H10B43/27

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel stack structure, a source pillar and a drain pillar, and a plurality of charge storage structures. The gate stack structure is located on the dielectric substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel stack structure extends through the gate stack structure. The channel stack structure includes a plurality of channel rings spaced apart from each other. The source pillar and the drain pillar are located in the channel stack structure and are respectively electrically connected to the plurality of channel rings. The plurality of charge storage structures are located between the plurality of gate layers and the plurality of channel rings.

公开(公告)号：US12022654B2

公开(公告)日：2024-06-25

申请号：US17185275

申请日：2021-02-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Guan-Ru Lee

IPC: H10B43/10 ,  H10B43/27

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.

公开(公告)号：US11476276B2

公开(公告)日：2022-10-18

申请号：US17102563

申请日：2020-11-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee

IPC: H01L27/1158 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.

公开(公告)号：US20220199639A1

公开(公告)日：2022-06-23

申请号：US17125407

申请日：2020-12-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles.

公开(公告)号：US20190148396A1

公开(公告)日：2019-05-16

申请号：US15814582

申请日：2017-11-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee

IPC: H01L27/11582 ,  H01L29/04 ,  H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L21/311 ,  H01L29/16 ,  H01L29/10

Abstract: A three-dimensional (3D) stacked semiconductor structure is provided. A substrate having an array area and a peripheral area is provided, and several patterned multi-layered stacks above the substrate are formed in the array area. The patterned multi-layered stacks are spaced apart from each other, and channel holes are formed between the patterned multi-layered stacks disposed adjacently. A charge trapping layer is formed on the patterned multi-layered stacks and deposited in the channel holes as liners. A polysilicon channel layer is deposited along the charge trapping layer, and conductive pads are formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks. The polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), wherein the second thickness (t2) is larger than the first thickness (t1).

公开(公告)号：US20180261620A1

公开(公告)日：2018-09-13

申请号：US15454103

申请日：2017-03-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee ,  Jia-Rong Chiou

IPC: H01L27/11582 ,  H01L27/11568

Abstract: A 3D memory device includes a multi-layer stack, a first contact layer, a memory layer, a cannel layer. The multi-layer stack includes a plurality of conductive layers, a first opening and a second opening. The conductive layers are vertical stacked and insulated with each other. The first opening and the second opening respectively penetrate through at least two adjacent ones of the conductive layers. The first contact layer is disposed in the first opening and electrically connecting the conductive layers penetrated by the first opening. The memory layer is disposed in the second opening. The channel layer covers on the memory layer, wherein a plurality of memory cells are formed at cross points of the channel layer, the memory layer and the conductive layers penetrated by the second opening.

公开(公告)号：US09401371B1

公开(公告)日：2016-07-26

申请号：US14863633

申请日：2015-09-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee ,  Chiajung Chiu

IPC: H01L21/336 ,  H01L29/76 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/764 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/768 ,  H01L27/11565

Abstract: A method for manufacturing a memory device, which can be configured as a 3D NAND flash memory, and includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

Abstract translation: 一种用于制造可被配置为3D NAND闪速存储器的存储器件的方法，并且包括多个堆叠的导电条，包括偶数堆叠和具有侧壁的奇数堆叠。 堆叠中的一些导电条被配置为字线。 数据存储结构设置在偶数和奇数堆栈的侧壁上。 在相应的偶数和奇数个导体条之间的有源支柱包括连接在堆叠之间的沟槽底部的偶数和奇数半导体膜，并具有外表面和内表面。 外表面接触形成存储器单元的3D阵列的对应偶数和奇数堆叠的侧壁上的数据存储结构; 内表面由可以包括间隙的绝缘结构隔开。 半导体膜可以是具有U形电流路径的薄膜。