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公开(公告)号：US11049557B2
公开(公告)日：2021-06-29
申请号：US16517485
申请日：2019-07-19
Applicant: Macronix International Co., Ltd.
Inventor： Yun-Chen Chou , Yung-Feng Lin , Hsin-Yi Ho
Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.
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12.发明申请公开(公告)号：US20170076797A1
公开(公告)日：2017-03-16
申请号：US15222861
申请日：2016-07-28
Inventor： Hsiang-Lan Lung , Hsin-Yi Ho , Scott C. Lewis , RICHARD C. JORDAN
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C7/1039 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069
Abstract: A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.
Abstract translation: 提供被配置为从其读取数据的存储器。 存储器包括包括并行设置的B个发射机和用于在时钟的上升沿和下降沿传送数据的数据端口，包括第一数据总线的第一存储器，所述第一数据总线包括可以传送N位的N行;以及第二存储器， 包括可以传送N位的N行的第二数据总线。 存储器包括数据路径控制器，其包括设置在第一和第二存储器之间并连接到数据端口的数据分配器，其中在上升沿，数据分配器从第一数据总线分配由B位组成的第一数据段 并且在下降沿，数据分配器将由B位组成的第二数据段从第二数据总线分配到数据端口。
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公开(公告)号：US11711926B2
公开(公告)日：2023-07-25
申请号：US17026036
申请日：2020-09-18
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho
CPC classification number: H10B63/80 , H10B63/20 , H10B63/30 , H10N70/231
Abstract: A memory array and structure are provided. The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements.
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公开(公告)号：US20210020235A1
公开(公告)日：2021-01-21
申请号：US16517485
申请日：2019-07-19
Applicant: Macronix International Co., Ltd.
Inventor： Yun-Chen Chou , Yung-Feng Lin , Hsin-Yi Ho
Abstract: A mechanism is described for accommodating variations in the read or write window which are caused by variations in the number of half-selected cells which are in each logic state and share an access line with the target cell. Roughly described, leakage current is detected on the access line in one segment of the read or write operation, and read or write current detected or generated in a second segment of the operation is adjusted to compensate for the detected leakage current. The first segment can be omitted in subsequent read or write operations if the target cell word line address has not changed and the leakage-tracked reference value has not become invalid for other reasons.
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公开(公告)号：US09507663B1
公开(公告)日：2016-11-29
申请号：US14703183
申请日：2015-05-04
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho , Hsiang-Lan Lung , Wei-Chih Chien , Tu-Shun Chen , Chia-Jung Chen
CPC classification number: G06F3/0683 , G06F3/0619 , G06F3/064 , G06F11/1048
Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.
Abstract translation: 提供了一种存储器件及其操作方法，并且存储器件的操作方法包括以下步骤。 执行编程操作以将原始数据写入存储器件中的第一存储器阵列。 验证第一存储器阵列中的原始数据，并根据验证结果确定是否生成写入信号。 根据原始数据生成纠错码，并将纠错码和写入地址临时存储在存储装置的缓冲电路中。 当产生写入信号时，将缓冲电路中的纠错码和写入地址写入存储器件中的第二存储器阵列。
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Patent Agency Ranking
公开(公告)号：US20220093686A1
公开(公告)日：2022-03-24
申请号：US17026036
申请日：2020-09-18
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho
Abstract: A memory array and structure are provided The array includes driving elements arranged in array; memory cells arranged in array and respectively corresponding to the driving elements, where one end of each memory cell is coupled to a first end of the corresponding driving element; word lines and bit lines arranged to intersect with each other, where each word lines is coupled to control ends of the driving elements in the same word line, and each bit line is respectively coupled to the other ends of the memory cells. For each word line, the first end of one driving element is connected to the first end of at least one other driving element in the same word line by a metal line, so as to form share driving elements.
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公开(公告)号：US20210035644A1
公开(公告)日：2021-02-04
申请号：US16529553
申请日：2019-08-01
Applicant: Macronix International Co., Ltd.
Inventor： WEI-CHIH CHIEN , Hsin-Yi Ho , Hsiang-Lan Lung
Abstract: A memory apparatus and a data access method for a memory are provided. The data access method includes: receiving a data erase command for performing a data erase operation; and, during the data erase operation: configuring a selected memory cell block in the memory according to the data erase command; providing a flag memory cell corresponding to the selected memory cell block, erasing a data in the flag memory cell according to the data erase command, and keeping a data in a plurality of selected memory cells in the selected memory cell block unchanged.
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公开(公告)号：US09779813B2
公开(公告)日：2017-10-03
申请号：US15222861
申请日：2016-07-28
Inventor： Hsiang-Lan Lung , Hsin-Yi Ho , Scott C. Lewis , Richard C. Jordan
CPC classification number: G11C13/0097 , G11C7/1039 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069
Abstract: A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.
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公开(公告)号：US20160328288A1
公开(公告)日：2016-11-10
申请号：US14703183
申请日：2015-05-04
Applicant: MACRONIX International Co., Ltd.
Inventor： Hsin-Yi Ho , Hsiang-Lan Lung , Wei-Chih Chien , Tu-Shun Chen , Chia-Jung Chen
CPC classification number: G06F3/0683 , G06F3/0619 , G06F3/064 , G06F11/1048
Abstract: A memory device and an operation method thereof are provided, and the operation method of the memory device includes following steps. A programming operation is performed to write an original data into a first memory array in the memory device. The original data in the first memory array is verified, and whether to generate a write signal is determined according to a verification result. An error correction code is generated according to the original data, and the error correction code and a write address are stored temporarily in a buffer circuit of the memory device. When the write signal is generated, the error correction code and the write address in the buffer circuit are written into a second memory array in the memory device.
Abstract translation: 提供了一种存储器件及其操作方法，并且存储器件的操作方法包括以下步骤。 执行编程操作以将原始数据写入存储器件中的第一存储器阵列。 验证第一存储器阵列中的原始数据，并根据验证结果确定是否生成写入信号。 根据原始数据生成纠错码，并将纠错码和写入地址临时存储在存储装置的缓冲电路中。 当产生写入信号时，将缓冲电路中的纠错码和写入地址写入存储器件中的第二存储器阵列。
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20.发明授权公开(公告)号：US09152557B2
公开(公告)日：2015-10-06
申请号：US14265400
申请日：2014-04-30
Applicant: Macronix International Co., Ltd.
Inventor： Lung-Yi Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen
CPC classification number: G06F12/0246 , G06F11/00 , G06F2212/7201 , G06F2212/7203 , G11C16/10 , G11C16/105 , G11C2211/5648
Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.
Abstract translation: 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。
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