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    Semiconductor apparatus and manufacturing method of the same
    11.
    发明授权
    Semiconductor apparatus and manufacturing method of the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09293471B1

    公开(公告)日：2016-03-22

    申请号：US14524066

    申请日：2014-10-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L29/49 ,  H01L21/768 ,  H01L29/792

    CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/76816 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4975 ,  H01L29/7926

    Abstract: A semiconductor apparatus including a first stacked structure and a second stacked structure is provided. The first stacked structure and the second stacked structure are arranged along a first direction, and extended along a second direction perpendicular to the first direction. The first stacked structure includes a first operating portion and a first supporting portion. The first operating portion and the first supporting portion are alternately arranged along the second direction. A width of the first operating portion along the first direction is smaller than a width of the first supporting portion along the first direction.

    Abstract translation: 提供了包括第一堆叠结构和第二堆叠结构的半导体装置。 第一堆叠结构和第二堆叠结构沿着第一方向布置，并且沿着垂直于第一方向的第二方向延伸。 第一堆叠结构包括第一操作部分和第一支撑部分。 第一操作部分和第一支撑部分沿着第二方向交替布置。 沿着第一方向的第一操作部的宽度小于第一支撑部沿着第一方向的宽度。

    SEMICONDUCTOR STRUCTURE
    13.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权
    半导体结构

    公开(公告)号：US20150155388A1

    公开(公告)日：2015-06-04

    申请号：US14093072

    申请日：2013-11-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L29/788 ,  H01L27/115

    CPC classification number: H01L27/11556 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/11578

    Abstract: A semiconductor device comprises a plurality of stacking blocks and a plurality of conductive lines. Each stacking blocks comprises two opposite finger VG structures. Each finger VG structure includes a staircase structure and a plurality of bit line stacks. The staircase structure is perpendicular to the bit line stacks, and the bit line stacks of the two opposite finger VG structures are arranged alternately. The conductive lines is disposed over the stacking blocks at interval The direction of the conductive lines is parallel to a direction of the bit line stacks. The conductive lines include a plurality of bit lines and a plurality of ground lines, and each stacking block includes at least one ground line.

    Abstract translation: 半导体器件包括多个堆叠块和多个导电线。 每个堆叠块包括两个相对的手指VG结构。 每个手指VG结构包括阶梯结构和多个位线堆叠。 梯形结构垂直于位线堆叠，并且两个相对的手指VG结构的位线堆叠交替布置。 导电线以间隔设置在堆叠块上方。导线的方向平行于位线堆叠的方向。 导线包括多个位线和多个接地线，并且每个堆叠块包括至少一个接地线。

    Memory device structure with page buffers in a page-buffer level separate from the array level
    14.
    发明授权
    Memory device structure with page buffers in a page-buffer level separate from the array level 有权
    存储器设备结构，页面缓冲区中的页面缓冲区与数组级别分开

    公开(公告)号：US09047953B2

    公开(公告)日：2015-06-02

    申请号：US13973774

    申请日：2013-08-22

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: G11C16/16 ,  G11C16/04 ,  H01L27/115 ,  G11C16/10

    CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C7/1006 ,  G11C11/4097 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C2029/0411 ,  G11C2207/005 ,  G11C2207/2245 ,  H01L27/11578

    Abstract: A structure of a memory device and a method for making the memory device structure are described. The memory device includes an array of memory cells in an array level die. The array comprises a plurality of sub-arrays. Each of the sub-arrays comprises respective data lines. The memory device also includes page buffers for corresponding sub-arrays in a page-buffer level die. The memory device also includes inter-die connections that are configured to electrically couple the page buffers in the page-buffer level die to data lines of corresponding sub-arrays in the array level die.

    Abstract translation: 描述存储器件的结构和用于制造存储器件结构的方法。 存储器件包括阵列级管芯中的存储器单元的阵列。 阵列包括多个子阵列。 每个子阵列包括相应的数据线。 存储器装置还包括页缓冲器级芯片中的相应子阵列的页缓冲器。 存储器装置还包括管芯间连接，其被配置为将页缓冲器级管芯中的页缓冲器电耦合到阵列级管芯中的相应子阵列的数据线。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME
    15.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
    其半导体结构及其制造方法

    公开(公告)号：US20150145012A1

    公开(公告)日：2015-05-28

    申请号：US14091375

    申请日：2013-11-27

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L27/115 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/306

    CPC classification number: H01L27/11578 ,  H01L27/11206 ,  H01L27/11565 ,  H01L29/66833

    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked portion disposed along a first direction, at least one second stacked portion connected with the first stacked portion and disposed along a second direction perpendicular to the first direction, and at least one third stacked portion connected with the first direction and arranged alternately with the second stacked portion along the first direction. The width of the third stacked portion is smaller than the width of the second stacked portion along the second direction.

    Abstract translation: 提供半导体结构。 半导体结构包括第一堆叠结构。 第一堆叠结构包括沿着第一方向设置的第一堆叠部分，与第一堆叠部分连接并沿着垂直于第一方向的第二方向设置的至少一个第二堆叠部分，以及与第一堆叠部分连接的第一堆叠部分 方向并且沿着第一方向与第二堆叠部分交替布置。 第三堆叠部分的宽度小于沿着第二方向的第二堆叠部分的宽度。

    Three-dimensional memory structure and method of operating the same hydride
    17.
    发明授权
    Three-dimensional memory structure and method of operating the same hydride 有权
    三维记忆结构和操作方法相同的氢化物

    公开(公告)号：US08659949B1

    公开(公告)日：2014-02-25

    申请号：US13729092

    申请日：2012-12-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Shih-Hung Chen

    IPC: G11C11/34

    CPC classification number: H01L27/11582 ,  H01L27/1157

    Abstract: A three-dimensional memory structure is provided, comprising plural stacked structures vertically formed on a substrate, each stacked structure comprising a bottom gate, wherein the bottom gates of the stacked structures are electrically connected; plural gates and gate insulators alternately stacked on the bottom gate; and two selection lines formed above the gates and spaced apart form each other and the selection lines being independently controlled, wherein the gate insulator fills between the selection lines, between the gate and the selection lines and forms on top of the selection lines for insulation. The 3D memory structure further comprises plural charge trapping multilayers formed outsides of the stacked structures and extending to the bottom gates; plural ultra-thin channels formed outsides of the charge trapping multilayers and lined between the adjacent stacked structures; and a dielectric layer formed between the ultra-thin channels and between the stacked structures.

    Abstract translation: 提供三维记忆结构，其包括垂直形成在基底上的多个层叠结构，每个堆叠结构包括底部门，其中堆叠结构的底部门电连接; 多个栅极和栅绝缘体交替堆叠在底栅上; 并且形成在栅极上方并彼此间隔开并且独立地控制选择线的两条选择线，其中栅极绝缘体填充在栅极和选择线之间的选择线之间并且形成在用于绝缘的选择线之上。 3D存储器结构还包括形成在层叠结构的外侧并延伸到底栅的多个电荷俘获多层; 多个超薄通道形成电荷捕获多层的外部并排列在相邻堆叠结构之间; 以及形成在超薄通道之间和堆叠结构之间的电介质层。

    3D NAND word line connection structure
    18.
    发明授权
    3D NAND word line connection structure 有权

    公开(公告)号：US10833015B2

    公开(公告)日：2020-11-10

    申请号：US16879541

    申请日：2020-05-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

    Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

    3D NAND WORD LINE CONNECTION STRUCTURE
    19.
    发明申请
    3D NAND WORD LINE CONNECTION STRUCTURE 审中-公开

    公开(公告)号：US20200279810A1

    公开(公告)日：2020-09-03

    申请号：US16879541

    申请日：2020-05-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11575

    Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

    3D NAND world line connection structure
    20.
    发明授权
    3D NAND world line connection structure 有权

    公开(公告)号：US10700004B2

    公开(公告)日：2020-06-30

    申请号：US15960106

    申请日：2018-04-23

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Hung Chen

    IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A memory device comprises a stack of linking elements including a first group of linking elements and a second group of linking elements different than the first group of linking elements. Interlayer connectors in a first plurality of interlayer connectors are connected to respective linking elements in the first group of linking elements. Interlayer connectors in a second plurality of interlayer connectors are connected to linking elements in the second group of linking elements. Patterned conductor lines in a first layer of patterned conductor lines are coupled to respective interlayer connectors in the first plurality of interlayer connectors. Patterned conductor lines in a second layer of patterned conductor lines disposed higher than the first layer of patterned conductor lines are coupled to respective interlayer connectors in the second plurality of interlayer connectors.

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