公开(公告)号：US20160197041A1

公开(公告)日：2016-07-07

申请号：US14589006

申请日：2015-01-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Sheng-Chih Lai ,  Wei-Chen Chen

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/115 ,  H01L23/532

CPC classification number: H01L21/28282 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a first conductive stripe, a first memory layer, a first conductive pillar, a first dielectric layer and a first conductive plug. The first conductive strip extends along a first direction. The first memory layer extends along a second direction adjacent to and overlapping with the first conductive stripe to define a first memory area thereon. The first conductive pillar extends along the second direction and overlapping with the first memory area. The first dielectric layer extends along the second direction adjacent to the first conductive stripe, the first memory layer and the first conductive pillar. The first conductive plus extends along the second direction and at least overlaps with a portion of the first conductive stripe, wherein the first conductive plus is electrically insulated from the first conductive stripe, the first memory layer and the first conductive pillar by the first dielectric layer.

Abstract translation: 存储器件包括第一导电条，第一存储层，第一导电柱，第一介电层和第一导电插塞。 第一导电条沿着第一方向延伸。 第一存储层沿着与第一导电条相邻并与其重叠的第二方向延伸以在其上限定第一存储区。 第一导电柱沿着第二方向延伸并与第一存储区重叠。 第一电介质层沿着与第一导电条，第一存储层和第一导电柱相邻的第二方向延伸。 第一导电加极沿着第二方向延伸并且至少与第一导电条的一部分重叠，其中第一导电加上与第一导电条电绝缘，第一存储层和第一导电柱由第一介电层 。

公开(公告)号：US09252155B2

公开(公告)日：2016-02-02

申请号：US14309923

申请日：2014-06-20

Applicant: Macronix International Co., Ltd.

Inventor： Tzu-Hsuan Hsu ,  Wei-Chen Chen ,  Hang-Ting Lue

IPC: H01L23/52 ,  H01L27/115 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/225 ,  H01L21/285

CPC classification number: H01L21/28525 ,  H01L21/2257 ,  H01L23/53271 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer. A width of the second electrode layer becomes larger in a direction away from the dielectric layer.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括在第一电极层和第二电极层之间的第一电极层，第二电极层和电介质层。 第二电极层的宽度在远离电介质层的方向上变大。

公开(公告)号：US12245413B2

公开(公告)日：2025-03-04

申请号：US17695943

申请日：2022-03-16

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng-Hao Yeh

IPC: H01L27/11 ,  H10B10/00

Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.

公开(公告)号：US20240407151A1

公开(公告)日：2024-12-05

申请号：US18636270

申请日：2024-04-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: H10B12/00 ,  G11C5/06

Abstract: A memory cell circuit, a memory cell array structure and a manufacturing method thereof are provided. The memory cell circuit includes a first transistor, a second transistor and a capacitor. The first transistor has a first end electrically coupled to a bit line, and a gate of the first transistor is electrically coupled to a primary word line. The second transistor has a first end electrically coupled to a second end of the first transistor, and a gate of the second transistor is electrically coupled to an auxiliary word line. A first end of the capacitor is electrically coupled to a second end of the second transistor and a second end of the capacitor receives a reference voltage.

公开(公告)号：US11825653B2

公开(公告)日：2023-11-21

申请号：US16923144

申请日：2020-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H10B43/27 ,  H01L29/06 ,  H01L29/423 ,  H10B43/10 ,  H10B43/30 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: H10B43/27 ,  H01L29/0649 ,  H01L29/42344 ,  H10B43/10 ,  H10B43/30 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first portion and a second portion of the channel layer. The first portion is opposite to the second portion. The first portion is surrounded by the memory structure, and the second portion is exposed from the memory structure.

公开(公告)号：US11800697B2

公开(公告)日：2023-10-24

申请号：US17005550

申请日：2020-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: H01L21/00 ,  H10B12/00 ,  G11C11/56 ,  G11C11/39 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B12/00 ,  G11C11/39 ,  G11C11/5621 ,  G11C11/5671 ,  H10B41/27 ,  H10B43/27

Abstract: A memory structure is provided. The memory structure includes a first channel body, a first source region, a first drain region, a first gate structure and a second gate structure. The first source region has a first conductivity and connects to a first end of the first channel body. The first drain region has a second conductivity and connects to a second end of the first channel body separated from the first end. The first gate structure is disposed adjacent to the first channel body and between the first end and the second end. The second gate structure disposed adjacent to the first channel body and between the first end and the second end.

公开(公告)号：US11678486B2

公开(公告)日：2023-06-13

申请号：US16784167

申请日：2020-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen ,  Teng Hao Yeh ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51 ,  H01L21/306 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

公开(公告)号：US10276250B1

公开(公告)日：2019-04-30

申请号：US15818208

申请日：2017-11-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/12 ,  H01L27/11524 ,  H01L27/1157

Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

公开(公告)号：US09379129B1

公开(公告)日：2016-06-28

申请号：US14685420

申请日：2015-04-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L27/105 ,  H01L27/115 ,  H01L23/528 ,  H01L21/265

CPC classification number: H01L21/26586 ,  H01L21/26513 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578

Abstract: A 3D array of memory cells with one or more blocks is described. The blocks include a plurality of layers. The layers in the plurality include semiconductor strips which extend from a semiconductor pad. The layers are disposed so that the semiconductor strips in the plurality of layers form a plurality of stacks of semiconductor strips and a stack of semiconductor pads. Also, a plurality of select gate structures are disposed over stacks of semiconductor strips in the plurality of stacks between the semiconductor pad and memory cells on the semiconductor strips. In addition, different ones of the plurality of select gate structures couple the semiconductor strips in different ones of the stacks of semiconductor strips to the semiconductor pads in the plurality of layers. Further, an assist gate structure is disposed over the plurality of stacks between the select gate structures and the stack of semiconductor pads.

Abstract translation: 描述具有一个或多个块的存储器单元的3D阵列。 这些块包括多个层。 多个层中的层包括从半导体衬垫延伸的半导体条。 这些层被设置成使得多个层中的半导体条形成多个半导体条的叠层和一叠半导体焊盘。 此外，多个选择栅极结构设置在半导体衬底和半导体条上的存储单元之间的多个堆叠中的半导体条的堆叠之上。 此外，多个选择栅极结构中的不同的选择栅极结构将半导体条的不同堆叠中的半导体条耦合到多个层中的半导体焊盘。 此外，辅助栅极结构设置在选择栅极结构和半导体焊盘堆之间的多个堆叠之上。

公开(公告)号：US20160141300A1

公开(公告)日：2016-05-19

申请号：US14541169

申请日：2014-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Wei-Chen Chen

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11575

Abstract: A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a source region and a drain region disposed separately. The source region comprises a first source region and a second source region disposed between the first source region and the drain region. The first source region is p-type of doping, the second source region is n-type of doping, and the drain region is n-type of doping.

Abstract translation: 公开了一种三维（3D）存储器及其制造方法。 根据一个实施例，3D存储器包括薄膜晶体管。 薄膜晶体管具有单独设置的源极区域和漏极区域。 源极区域包括设置在第一源极区域和漏极区域之间的第一源极区域和第二源极区域。 第一源区是p型掺杂，第二源区是n型掺杂，漏区是n型掺杂。