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    Memory device and programming method of multi-level cell (MLC)
    11.
    发明授权
    Memory device and programming method of multi-level cell (MLC) 有权

    公开(公告)号：US10748605B2

    公开(公告)日：2020-08-18

    申请号：US16057871

    申请日：2018-08-08

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yung-Chun Li ,  Ping-Hsien Lin

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

    Abstract: Provided is a programming method for a memory device including a memory array and a controller. The programming method including: controlling programming on a first page of a first word line by the controller; controlling programming on a first page of a second word line by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line by the controller; controlling programming on a first page of a third word line by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line by the controller; and controlling for performing a second programming operation on the second page of the first word line by the controller.

    DATA MANAGEMENT METHOD FOR MEMORY AND MEMORY APPARATUS
    12.
    发明申请
    DATA MANAGEMENT METHOD FOR MEMORY AND MEMORY APPARATUS 审中-公开

    公开(公告)号：US20190087110A1

    公开(公告)日：2019-03-21

    申请号：US15705309

    申请日：2017-09-15

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yung-Chun Li ,  Ping-Hsien Lin ,  Yu-Ming Chang

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0688 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3418

    Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.

    MEMORY DISTURB REDUCTION FOR NONVOLATILE MEMORY
    14.
    发明申请
    MEMORY DISTURB REDUCTION FOR NONVOLATILE MEMORY 有权
    非易失性存储器的存储器干扰减少

    公开(公告)号：US20140307505A1

    公开(公告)日：2014-10-16

    申请号：US14060296

    申请日：2013-10-22

    Applicant: Macronix International Co., Ltd

    Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

    IPC: G11C16/34

    CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

    Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

    Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。

    Memory device and operation method thereof
    17.
    发明授权
    Memory device and operation method thereof 有权

    公开(公告)号：US11656988B2

    公开(公告)日：2023-05-23

    申请号：US17542557

    申请日：2021-12-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Han-Wen Hu ,  Yung-Chun Li ,  Bo-Rong Lin ,  Huai-Mu Wang

    IPC: G06F12/00 ,  G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/1024

    Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

    IN-MEMORY COMPUTING METHOD AND IN-MEMORY COMPUTING APPARATUS
    18.
    发明申请
    IN-MEMORY COMPUTING METHOD AND IN-MEMORY COMPUTING APPARATUS 有权

    公开(公告)号：US20220075601A1

    公开(公告)日：2022-03-10

    申请号：US17411938

    申请日：2021-08-25

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Bo-Rong Lin ,  Yung-Chun Li ,  Han-Wen Hu ,  Huai-Mu Wang

    IPC: G06F7/544 ,  G06F7/74 ,  G11C7/06 ,  G11C7/10

    Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

    Data management method for memory and memory apparatus using the same
    19.
    发明授权
    Data management method for memory and memory apparatus using the same 有权

    公开(公告)号：US11222693B2

    公开(公告)日：2022-01-11

    申请号：US17035885

    申请日：2020-09-29

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yung-Chun Li ,  Wei-Chen Wang

    IPC: G11C16/34 ,  G11C11/56 ,  G06F12/02 ,  G11C16/10 ,  G11C16/16

    Abstract: A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.

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