公开(公告)号：US07671475B2

公开(公告)日：2010-03-02

申请号：US11764416

申请日：2007-06-18

申请人： Takeshi Kamigaichi ,  Takeshi Murata ,  Itaru Kawabata

发明人： Takeshi Kamigaichi ,  Takeshi Murata ,  Itaru Kawabata

IPC分类号： H01L29/41 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G11C5/06 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

摘要翻译： 非易失性半导体存储器包括具有选择栅极晶体管和串联连接的存储单元的单元单元，连接到选择栅极晶体管的选择栅极线和连接到存储单元的字线。 字线的一端弯曲到选择栅线侧，并且边缘连接在字线的弯曲点和远端之间。

公开(公告)号：US07369439B2

公开(公告)日：2008-05-06

申请号：US11397725

申请日：2006-04-05

申请人： Takeshi Kamigaichi ,  Kikuko Sugimae

发明人： Takeshi Kamigaichi ,  Kikuko Sugimae

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C2216/14 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of memory cell transistors arranged in a matrix form. The device further includes a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path which is connected at one end to a selected control gate and a second high-voltage transistor having a current path which is connected at one end to a first non-selected control gate adjacent to the selected control gate and configured to raise voltage applied to the selected control gate to program voltage by use of first capacitive coupling caused between the selected control gate and the first non-selected control gate by applying intermediate voltage approximately equal to voltage which makes the current path of the memory cell transistor conductive to the first non-selected control gate.

摘要翻译： 半导体集成电路器件包括具有以矩阵形式布置的多个存储单元晶体管的存储单元阵列。 该装置还包括布置在存储单元阵列的外围区域中的高压电路区域，并且包括具有电流路径的第一高压晶体管，该电流路径一端连接到选定的控制栅极和第二高压晶体管 具有电流路径，其一端连接到与所选择的控制栅极相邻的第一未选择的控制栅极，并且被配置为通过使用在所选择的控制栅极之间产生的第一电容耦合来提高施加到所选择的控制栅极的编程电压 以及通过施加近似等于使存储单元晶体管的电流路径导通到第一未选择的控制栅极的电压的中间电压而使第一未选择的控制栅极。

公开(公告)号：US20070057315A1

公开(公告)日：2007-03-15

申请号：US11556299

申请日：2006-11-03

申请人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

发明人： Michiharu MATSUI ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Takeshi Kamigaichi

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11543 ,  H01L29/7887

摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

公开(公告)号：US20060239069A1

公开(公告)日：2006-10-26

申请号：US11397725

申请日：2006-04-05

申请人： Takeshi Kamigaichi ,  Kikuko Sugimae

发明人： Takeshi Kamigaichi ,  Kikuko Sugimae

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C2216/14 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of memory cell transistors arranged in a matrix form. The device further includes a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path which is connected at one end to a selected control gate and a second high-voltage transistor having a current path which is connected at one end to a first non-selected control gate adjacent to the selected control gate and configured to raise voltage applied to the selected control gate to program voltage by use of first capacitive coupling caused between the selected control gate and the first non-selected control gate by applying intermediate voltage approximately equal to voltage which makes the current path of the memory cell transistor conductive to the first non-selected control gate.

摘要翻译： 半导体集成电路器件包括具有以矩阵形式布置的多个存储单元晶体管的存储单元阵列。 该装置还包括布置在存储单元阵列的外围区域中的高压电路区域，并且包括具有电流路径的第一高压晶体管，该电流路径一端连接到选定的控制栅极和第二高压晶体管 具有电流路径，其一端连接到与所选择的控制栅极相邻的第一未选择的控制栅极，并且被配置为通过使用在所选择的控制栅极之间产生的第一电容耦合来提高施加到所选择的控制栅极的编程电压 以及通过施加近似等于使存储单元晶体管的电流路径导通到第一未选择的控制栅极的电压的中间电压而使第一未选择的控制栅极。

公开(公告)号：US08751888B2

公开(公告)日：2014-06-10

申请号：US13237291

申请日：2011-09-20

申请人： Takeshi Kamigaichi ,  Kenji Sawamura

发明人： Takeshi Kamigaichi ,  Kenji Sawamura

IPC分类号： G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： G11C11/5628 ,  G06F1/305 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/3202

摘要： A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

摘要翻译： 控制电路通过对所选择的字线施加写脉冲电压，对所选字线对1页存储单元执行写操作，然后执行确认数据写入是否完成的验证读操作。 当数据写入未完成时，通过一定的升压电压来提高写入脉冲电压的升压动作。 位扫描电路根据读出放大器电路中保持的读取数据，确定在同时读取的存储单元中确定达到一定阈值电压的存储单元数是否等于或大于一定数量 的验证读取操作。 控制电路根据位扫描电路的判定来改变升压电压的量。

公开(公告)号：US08497582B2

公开(公告)日：2013-07-30

申请号：US13427061

申请日：2012-03-22

申请人： Takeshi Kamigaichi ,  Takeshi Murata ,  Itaru Kawabata

发明人： Takeshi Kamigaichi ,  Takeshi Murata ,  Itaru Kawabata

IPC分类号： H01L29/41 ,  H01L27/115

CPC分类号： H01L27/11519 ,  G11C5/06 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

公开(公告)号：US08497543B2

公开(公告)日：2013-07-30

申请号：US13234260

申请日：2011-09-16

申请人： Jun Ogi ,  Takeshi Kamigaichi ,  Tatsuo Izumi

发明人： Jun Ogi ,  Takeshi Kamigaichi ,  Tatsuo Izumi

IPC分类号： H01L29/76

CPC分类号： H01L27/11524 ,  H01L21/76229 ,  H01L21/7682

摘要： A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.

摘要翻译： 半导体存储器件包括半导体衬底，多个元件隔离，多个第一层叠体，第二层叠体和层间绝缘膜。 第一层叠体和第二层叠体之间的距离比相邻的第一层叠体的距离长。 在第一堆叠体之间的层间绝缘膜中形成第一空隙。 在第一层叠体和第二层叠体之间的层间绝缘膜中形成第二空隙。 并且，第二空隙的下端位于第一空隙的下端之上。

公开(公告)号：US08482095B2

公开(公告)日：2013-07-09

申请号：US13086478

申请日：2011-04-14

申请人： Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Takeshi Kamigaichi

发明人： Hiroyuki Kutsukake ,  Kikuko Sugimae ,  Takeshi Kamigaichi

IPC分类号： H01L21/76

CPC分类号： H01L27/11526 ,  G11C16/0408 ,  G11C16/08 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/404

摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

公开(公告)号：US08253188B2

公开(公告)日：2012-08-28

申请号：US12728788

申请日：2010-03-22

申请人： Takeshi Kamigaichi ,  Satoshi Nagashima ,  Kenji Aoyama

发明人： Takeshi Kamigaichi ,  Satoshi Nagashima ,  Kenji Aoyama

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11529 ,  H01L27/11519 ,  H01L27/11526

摘要： A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.

摘要翻译： 一种半导体存储装置，包括半导体衬底，第一绝缘体，层叠绝缘体，其包括具有比第一绝缘体的电荷多的固定电荷的第二绝缘体，单层绝缘体，半导体衬底和第一绝缘体之间的存储单元， 通过空腔部分从相邻的存储单元分离的单元，包括隧道绝缘体，电荷累积层，绝缘体和控制栅电极，在半导体衬底和第一绝缘体之间的第一选择栅极晶体管，第二选择栅极晶体管 在所述半导体衬底和所述第一绝缘体之间，在一个存储单元和所述第一选择栅极晶体管之间，并且与所述层叠绝缘体在其存储单元侧的第一侧面接触;以及所述半导体之间的高压外围电路晶体管 基板和第一绝缘体，并与一侧的单层绝缘体接触 面对。

公开(公告)号：US08237218B2

公开(公告)日：2012-08-07

申请号：US13226224

申请日：2011-09-06

申请人： Takeshi Murata ,  Takeshi Kamigaichi

发明人： Takeshi Murata ,  Takeshi Kamigaichi

IPC分类号： H01L29/792

CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.

摘要翻译： 非易失性半导体存储器件包括具有第一选择晶体管的第一堆叠单元和形成在半导体衬底上的第二选择晶体管和具有第一绝缘层的第二堆叠单元和在第一堆叠单元的上表面上交替堆叠的第一导电层。 第二堆叠单元包括与第一绝缘层和第一导电层的侧壁接触形成的第二绝缘层，与用于存储电荷的第二绝缘层接触形成的电荷存储层，形成为接触的第三绝缘层 与电荷存储层形成的第一半导体层以及与第三绝缘层接触形成的层叠方向延伸的第一半导体层，一端与第一选择晶体管的一个扩散层连接，另一端与扩散层连接 的第二选择晶体管。