DETERMINING AND ANALYZING INTEGRATED CIRCUIT YIELD AND QUALITY
    11.
    发明申请
    DETERMINING AND ANALYZING INTEGRATED CIRCUIT YIELD AND QUALITY 审中-公开
    确定和分析集成电路的质量和质量

    公开(公告)号:US20090210183A1

    公开(公告)日:2009-08-20

    申请号:US12415806

    申请日:2009-03-31

    Abstract: Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.

    Abstract translation: 本文公开了用于计算,分析和改进集成电路产量和质量的方法,装置和系统。 例如,在本文公开的一个示例性方法中,从设计用于电子设备中的功能使用的集成电路的处理测试响应中接收信息。 在该实施例中,该信息表示在集成电路测试期间观察到的集成电路故障以及导致集成电路故障的可能的产量限制因素。 通过统计分析接收的信息来确定集成电路中的一个或多个可能的屈服限制因素实际上引起集成电路故障的概率。 报告了一个或多个可能的屈服限制因素实际上导致集成电路故障的概率。 还公开了包括用于使计算机执行任何所述方法的计算机可执行指令的有形计算机可读介质。

    Sensor array using sail
    12.
    发明授权
    Sensor array using sail 有权
    传感器阵列使用帆

    公开(公告)号:US07470544B2

    公开(公告)日:2008-12-30

    申请号:US11138619

    申请日:2005-05-26

    Applicant: Manish Sharma

    Inventor: Manish Sharma

    CPC classification number: G01N27/4145 Y10T436/25

    Abstract: Provided is a sensor array and a method of forming the same. The sensor array includes an array of apertures etched into a 3D patterned resist layer to expose areas of one or more agents and/or reagents deposited on a substrate. The sensor is formed using a Self-Aligned Imprint Lithography (“SAIL”) method, a process that allows for a one-time deposition of all required materials followed by a series of etching/cleaning steps. The location of reagents on the sensor template, as well as the concentration gradient of each reagent, may be controlled through the sensor manufacturing process. Bores of a single reagent, or bores containing two or more reagents, may be formed using the SAIL process.

    Abstract translation: 提供一种传感器阵列及其形成方法。 传感器阵列包括刻蚀成3D图案化抗蚀剂层的孔的阵列,以暴露沉积在基底上的一种或多种试剂和/或试剂的区域。 传感器使用自对准印迹光刻(“SAIL”)方法形成,该方法允许一次性沉积所有所需材料,然后进行一系列蚀刻/清洁步骤。 传感器模板上的试剂位置以及各试剂的浓度梯度可通过传感器制造过程进行控制。 可以使用SAIL方法形成单个试剂的孔或包含两种或更多种试剂的孔。

    Multi-layered magnetic memory structures
    13.
    发明授权
    Multi-layered magnetic memory structures 有权
    多层磁记忆体结构

    公开(公告)号:US07391641B2

    公开(公告)日:2008-06-24

    申请号:US11285991

    申请日:2005-11-23

    CPC classification number: G11C11/15 H01L27/222 H01L43/08

    Abstract: An exemplary memory array including a plurality of memory cells, each of the memory cells comprises a first ferromagnetic layer, a second ferromagnetic layer spaced apart from the first ferromagnetic layer by a non-magnetic separating layer and being magnetically coupled to the first ferromagnetic layer by demagnetizing fields from the first ferromagnetic layer, a spacer layer above the second ferromagnetic layer, and a reference layer above the spacer layer. The first ferromagnetic layer, non-magnetic separating layer, and second ferromagnetic layer in combination function as a data layer of the memory cell.

    Abstract translation: 包括多个存储器单元的示例性存储器阵列,每个存储器单元包括第一铁磁层,通过非磁性分离层与第一铁磁层隔开的第二铁磁层,并且通过非磁性分离层磁耦合到第一铁磁层,并通过 来自第一铁磁层的去磁场,第二铁磁层上方的间隔层,以及间隔层上方的基准层。 第一铁磁层,非磁性分离层和第二铁磁层组合起来作为存储单元的数据层。

    Device for forming magnetic well for nanoparticles
    14.
    发明申请
    Device for forming magnetic well for nanoparticles 有权
    用于形成纳米颗粒的磁性井的装置

    公开(公告)号:US20070122898A1

    公开(公告)日:2007-05-31

    申请号:US11290879

    申请日:2005-11-30

    Applicant: Manish Sharma

    Inventor: Manish Sharma

    CPC classification number: G01N35/0098 Y10S977/962

    Abstract: A device includes a plurality of structures, each structure including at least one ferromagnetic layer having fringe fields. Fringe fields of the structures interact to form a magnetic well for nanoparticles. This device may be adapted for biosensing, wherein the magnetic well is formed about a probe area.

    Abstract translation: 一种装置包括多个结构,每个结构包括至少一个具有边缘场的铁磁层。 结构的边缘相互作用以形成纳米颗粒的磁性井。 该装置可以适于生物传感,其中磁性阱围绕探针区域形成。

    Direct logic diagnostics with signature-based fault dictionaries
    15.
    发明申请
    Direct logic diagnostics with signature-based fault dictionaries 有权
    直接逻辑诊断与基于签名的故障字典

    公开(公告)号:US20070038911A1

    公开(公告)日:2007-02-15

    申请号:US11497977

    申请日:2006-08-01

    CPC classification number: G01R31/31703

    Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

    Abstract translation: 这里公开了用于在电路测试期间创建的签名执行诊断的方法,装置和系统的代表性实施例。 例如,在本文公开的一个示例性方法中,接收由签名生成器生成的签名。 在本实施例中,签名对应于电路对不超过一个测试图案的响应。 将签名与故障字典的条目进行比较,如果条目标识了解释签名的故障,则故障字典的条目与签名相匹配,并且故障存储在故障候选列表中。

    System and method for improved IMEI registration
    16.
    发明授权
    System and method for improved IMEI registration 失效
    改进IMEI注册的系统和方法

    公开(公告)号:US07139573B2

    公开(公告)日:2006-11-21

    申请号:US11098259

    申请日:2005-04-04

    CPC classification number: H04W8/245 H04W8/12

    Abstract: Methods and systems for IMEI registration are provided. In accordance with exemplary embodiments of the present invention, when an IMEI registration fails due to a network failure, the mobile station implements a back-off algorithm for future IMEI registration attempts. Specifically, the present invention provides a back-off algorithm which determines a different amount of time for the time period between each unsuccessful IMEI registration.

    Abstract translation: 提供IMEI注册的方法和系统。 根据本发明的示例性实施例,当IMEI注册由于网络故障而失败时,移动台实现用于将来的IMEI注册尝试的退避算法。 具体而言,本发明提供一种退避算法,其确定在每个不成功的IMEI注册之间的时间段内的不同的时间量。

    Process for making a memory structure
    17.
    发明授权
    Process for making a memory structure 有权
    制作内存结构的过程

    公开(公告)号:US07138341B1

    公开(公告)日:2006-11-21

    申请号:US10886963

    申请日:2004-07-07

    Applicant: Manish Sharma

    Inventor: Manish Sharma

    CPC classification number: H01L21/31144 H01L21/32139 H01L27/222 H01L43/12

    Abstract: An exemplary method for making a memory structure comprises forming a first hard mask layer, forming at least one mask layer above the first hard mask layer, patterning the at least one mask layer, etching the at least one mask layer to form an opening having a first lateral width, and a second lateral width different than the first lateral width, forming a second hard mask layer having substantially the first and second lateral widths in the opening, and etching the first hard mask layer using at least one of the lateral widths of the second hard mask layer.

    Abstract translation: 用于制造存储器结构的示例性方法包括形成第一硬掩模层,在第一硬掩模层上方形成至少一个掩模层,图案化至少一个掩模层,蚀刻至少一个掩模层以形成具有 第一横向宽度和与第一横向宽度不同的第二横向宽度,形成在开口中具有基本上第一和第二横向宽度的第二硬掩模层,并且使用横向宽度的至少一个来蚀刻第一硬掩模层 第二个硬掩模层。

    Cross point resistive memory array
    19.
    发明授权
    Cross point resistive memory array 有权
    交叉点电阻式存储器阵列

    公开(公告)号:US07002197B2

    公开(公告)日:2006-02-21

    申请号:US10814094

    申请日:2004-03-30

    CPC classification number: H01L27/224 G11C11/16 H01L27/24

    Abstract: A cross point resistive memory array has a first array of cells arranged generally in a plane. Each of the memory cells includes a memory storage element and is coupled to a diode. The diode junction extends transversely to the plane of the array of memory cells.

    Abstract translation: 交叉点电阻存储器阵列具有通常布置在平面中的第一阵列阵列。 每个存储单元包括存储器存储元件并且耦合到二极管。 二极管结横向延伸到存储单元阵列的平面。

    Forming a contact in a thin-film device
    20.
    发明授权
    Forming a contact in a thin-film device 失效
    在薄膜装置中形成接触

    公开(公告)号:US06989327B2

    公开(公告)日:2006-01-24

    申请号:US10770083

    申请日:2004-01-31

    Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the liftoff stencil and depositing a conductor material in contact with the at least one material on the re-entrant profile.

    Abstract translation: 本发明的一个方面是在薄膜器件中形成接触的方法。 该方法包括形成剥离模板,将至少一种材料沉积通过剥离模板,去除剥离模板的一部分,与剥离模板的剩余部分形成重新进入的模型并且沉积导体材料与所述脱模模板接触。 至少一个材料在入口轮廓。

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