公开(公告)号：US20070141660A1

公开(公告)日：2007-06-21

申请号：US11704279

申请日：2007-02-08

Applicant: Gopal Chotani ,  Manoj Kumar ,  Jeff Pucci ,  Karl Sanford ,  Jayarama Shetty

Inventor： Gopal Chotani ,  Manoj Kumar ,  Jeff Pucci ,  Karl Sanford ,  Jayarama Shetty

IPC: C12P1/00

CPC classification number: C12P7/56 ,  C12P7/06 ,  C12P7/10 ,  C12P7/18 ,  C12P7/20 ,  C12P7/42 ,  C12P7/44 ,  C12P7/46 ,  C12P7/58 ,  C12P7/60 ,  C12P19/02 ,  C12P2201/00 ,  Y02E50/16 ,  Y02E50/17

Abstract: The present invention provides means for the production of desired end-products of in vitro and/or in vivo bioconversion of biomass-based feed stock substrates, including but not limited to such materials as starch and cellulose. In particularly preferred embodiments, the methods of the present invention do not require gelatinization and/or liquefaction of the substrate.

Abstract translation: 本发明提供了生产基于生物质的原料基质的体外和/或体内生物转化所需的终产物的方法，包括但不限于淀粉和纤维素等材料。 在特别优选的实施方案中，本发明的方法不需要基质的凝胶化和/或液化。

公开(公告)号：US07229811B2

公开(公告)日：2007-06-12

申请号：US10343369

申请日：2001-08-03

Applicant: Manoj Kumar ,  Fernando Valle ,  Veronique A. Dartois ,  James A. Hoch

Inventor： Manoj Kumar ,  Fernando Valle ,  Veronique A. Dartois ,  James A. Hoch

IPC: C07H21/04 ,  C12N15/00 ,  C12N1/20 ,  C12P7/40 ,  C12P21/06 ,  C12Q1/26 ,  C07K14/00 ,  C12P19/34 ,  C12N9/04

CPC classification number: C07K14/26 ,  C07K14/24

Abstract: The invention provides isolated nucleic acid molecules encoding polypeptides having 2,5-DKG permease activity, and oligonucleotides therefrom. The isolated nucleic acid molecules can be expressed in appropriate bacterial cells to enhance the production of 2-KLG, which can subsequently be converted to ascorbic acid. Further provided are isolated polypeptides having 2,5-DKG permease acitivity, immunogenic peptides therefrom, and antibodies specific therefor. The invention also provides methods of identifying novel 2,5-DKG permeases.

Abstract translation: 本发明提供了编码具有2,5-DKG通透酶活性的多肽的分离的核酸分子及其寡核苷酸。 分离的核酸分子可以在适当的细菌细胞中表达以增强2-KLG的产生，随后将其转化为抗坏血酸。 还提供了具有2,5-DKG通透酶活性的分离的多肽，其免疫原性肽及其特异的抗体。 本发明还提供鉴定新型2,5-DKG通透酶的方法。

公开(公告)号：US20060153791A1

公开(公告)日：2006-07-13

申请号：US11351712

申请日：2006-02-10

Applicant: Katherine Collier ,  William Cuevas ,  Manoj Kumar

Inventor： Katherine Collier ,  William Cuevas ,  Manoj Kumar

IPC: A61K38/17 ,  A61K8/64 ,  C07K14/435

CPC classification number: A61K8/64 ,  A61K38/00 ,  A61K47/59 ,  A61K47/64 ,  A61K2800/57 ,  A61Q13/00 ,  A61Q17/04 ,  C07K14/21 ,  C07K14/415 ,  C07K14/43504 ,  C07K14/43586 ,  C07K14/4716 ,  C07K14/4727 ,  C07K14/4741 ,  C07K14/78 ,  C07K2319/00 ,  C08H1/00 ,  C08H1/06

Abstract: Biomolecular conjugates are provided which comprise the conjugation product of a repeat sequence protein polymer and at least one active agent. Additional aspects provide methods for their manufacture and various industrial and consumer applications.

Abstract translation: 提供了包含重复序列蛋白质聚合物和至少一种活性剂的缀合产物的生物分子缀合物。 其他方面提供了其制造方法和各种工业和消费者应用。

公开(公告)号：US20050112734A1

公开(公告)日：2005-05-26

申请号：US10842929

申请日：2004-05-10

Applicant: Timothy Dodge ,  Manoj Kumar ,  M. Rashid ,  Fernando Valle

Inventor： Timothy Dodge ,  Manoj Kumar ,  M. Rashid ,  Fernando Valle

IPC: C07K14/24 ,  C12N20060101 ,  C12N1/21 ,  C12N9/10 ,  C12P7/58 ,  C12P7/60 ,  C12P17/04

CPC classification number: C12P7/58 ,  C07K14/24 ,  C12P7/60

Abstract: The present invention relates to engineering metabolic pathways in bacterial host cells which results in enhanced carbon flow for the production of ascorbic acid (ASA) intermediates. In particular, the invention relates to increasing the production of ASA intermediates in bacterial cells by enhancing the availability of gluconate resulting from the inactivation of endogenous gluconate transporter genes.

Abstract translation: 本发明涉及在细菌宿主细胞中工程代谢途径，其导致用于生产抗坏血酸（ASA）中间体的增强的碳流。 特别地，本发明涉及通过增加由内源性葡萄糖酸转运蛋白基因失活产生的葡萄糖酸盐的可利用性来增加细菌细胞中ASA中间体的产生。

公开(公告)号：US06879198B2

公开(公告)日：2005-04-12

申请号：US10739879

申请日：2003-12-18

Applicant: Manoj Kumar ,  Rajesh Narwal

Inventor： Manoj Kumar ,  Rajesh Narwal

IPC: H03K3/3565 ,  H03K3/037

CPC classification number: H03K3/3565

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract translation: 具有参考电压两侧的迟滞的差分输入接收器可以包括双输入单输出差分放大器，其包括连接在一起的共同端子的两个输入晶体管。 每个晶体管的控制端可以连接到差分放大器的一个输入端。 差分放大器的输出可以连接到一组级联的数字反相器/缓冲器，并且每个数字缓冲器的输出可以连接到反馈晶体管的控制端子。 反馈晶体管可以并联连接在每个输入晶体管上，使得当一个输入电压在第二输入处增加到或低于第二输入处的输入电压以下预定阈值时，反馈晶体管操作以提供正反馈以促进快速 在输出端切换动作。

公开(公告)号：US06824996B2

公开(公告)日：2004-11-30

申请号：US10026139

申请日：2001-12-18

Applicant: Manoj Kumar

Inventor： Manoj Kumar

IPC: G01N3353

CPC classification number: C12P7/04 ,  C12N1/16

Abstract: The present invention provides for the production of ASA from yeast capable of producing ASA from KLG. The present invention provides methods for the production of ASA as well as recombinant yeast capable of producing ASA from a carbon source.

公开(公告)号：US6016534A

公开(公告)日：2000-01-18

申请号：US887825

申请日：1997-07-30

Applicant: Manoj Kumar ,  Huy Van Pham

Inventor： Manoj Kumar ,  Huy Van Pham

IPC: G11C11/419 ,  G11C15/04 ,  G06F13/00 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C15/04

Abstract: A cache memory device having circuitry for controlling operation of a sense amplifier for accessing an array in the data processing system including a cache memory device includes circuitry for enabling the sense amplifier when there is a hit in the array as a result of a read request and disables the sense amplifier when there is a miss in the array as a result of the read request. The cache memory device may receives an address associated with the read request, and compares the address to addresses associated with entries in the array, wherein a hit results when the received address matches at least one of the addresses associated with the entries in the array, and wherein a miss results when the received address does not match at least one of the addresses associated with the entries in the array. The address associated with the read request and the addresses associated with entries in the array are effective addresses. The cache memory device may enable the sense amp only when the array is being accessed by the read request, and only after an entire address associated with the read request has been received.

Abstract translation: 一种具有用于控制读取放大器的操作的电路的高速缓冲存储器件，该读出放大器用于访问数据处理系统中包括高速缓存存储器件的阵列，该电路包括用于当由于读取请求而在阵列中存在命中时能够使读出放大器工作的电路， 由于读取请求，当数组中存在缺失时，禁用读出放大器。 高速缓冲存储器设备可以接收与读取请求相关联的地址，并且将地址与与阵列中的条目相关联的地址进行比较，其中当接收到的地址匹配与阵列中的条目相关联的至少一个地址时， 并且其中当接收到的地址与与阵列中的条目相关联的至少一个地址不匹配时，导致未命中。 与读取请求相关联的地址和与数组中的条目相关联的地址是有效地址。 高速缓冲存储器装置可以仅在读取请求访问阵列时才能使能感测放大器，并且只有在已经接收到与读取请求相关联的整个地址之后才能使能该读出放大器。

公开(公告)号：US5959916A

公开(公告)日：1999-09-28

申请号：US19895

申请日：1998-02-06

Applicant: Manoj Kumar

Inventor： Manoj Kumar

IPC: G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/409 ,  G11C11/417 ,  G11C11/419 ,  G11C13/00 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C11/419 ,  G11C7/12

Abstract: A write driver apparatus (10) is adapted for producing a first data output signal and a second data output signal used in driving data onto a bit line pair (16, 18) associated with an electronic computer memory. The first and second data output signals represent desired data and are produced in response to a data signal, refill signal, and a data propagation clock signal. The data propagation signal is derived from system clock signals. A precharge circuit (12) associated with the write driver (10) operates in response to a precharge clock signal to precharge the bit lines (16, 18) prior to each read or write operation. The precharge clock signal is related to the data propagation signal to ensure that the bit lines (16, 18) are fully precharged prior to a read operation. A keeper circuit (14) associated with the bit lines (16, 18) also helps maintain a desired charge state on the bit lines during a read operation from memory cells (20) connected to the bit lines.

Abstract translation: 写驱动器装置（10）适用于产生用于将数据驱动到与电子计算机存储器相关联的位线对（16,18）上的第一数据输出信号和第二数据输出信号。 第一和第二数据输出信号表示期望的数据，并且响应于数据信号，再填充信号和数据传播时钟信号产生。 数据传播信号来源于系统时钟信号。 与写入驱动器（10）相关联的预充电电路（12）响应于预充电时钟信号而工作，以在每次读或写操作之前对位线（16,18）进行预充电。 预充电时钟信号与数据传播信号相关，以确保位线（16,18）在读取操作之前被完全预充电。 与位线（16,18）相关联的保持器电路（14）还有助于在连接到位线的存储器单元（20）的读取操作期间在位线上保持期望的电荷状态。

公开(公告)号：US5937429A

公开(公告)日：1999-08-10

申请号：US844550

申请日：1997-04-21

Applicant: Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

Inventor： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

IPC: G06F12/12

CPC classification number: G06F12/127

Abstract: A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

Abstract translation: 描述了具有可选择的高速缓存线更换方案的高速缓冲存储器。 根据本发明的优选实施例，高速缓冲存储器具有多个高速缓存线，多个令牌寄存器，令牌和选择电路。 令牌寄存器以环形配置相互连接。 存在相等数量的令牌寄存器和高速缓存行，并且每个令牌寄存器与其中一个高速缓存行相关联。 令牌被用于将一个缓存行指示为由令牌结算的相关联的令牌寄存器替换的候选。 选择电路与所有令牌寄存器相关联。 该选择电路提供至少两种方法来控制令牌在令牌寄存器的环内的移动，以便在运行时期间可选择。 令牌移动的每种方法代表高速缓存行替换方案。

公开(公告)号：US5915094A

公开(公告)日：1999-06-22

申请号：US866671

申请日：1997-06-02

Applicant: Jack Lawrence Kouloheris ,  Manoj Kumar

Inventor： Jack Lawrence Kouloheris ,  Manoj Kumar

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00 ,  H04H20/76 ,  H04H60/27 ,  H04L12/18 ,  H04N5/765 ,  H04N5/93 ,  H04N7/173 ,  H04N21/2312 ,  H04N21/238 ,  H04N21/262 ,  G06F13/38 ,  G06F15/17

CPC classification number: H04N21/2326 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0689 ,  H04N7/17336

Abstract: A method and apparatus for delivering multimedia video data from a server (host processor) to a plurality of clients connected to a communications network. More specifically, with this invention, preprocessed video and multimedia data packets are striped across disks in units of fixed playback time, even if such units result in variable length stripes. To deliver multiple video or continuous media streams, the disks in the array are accessed simultaneously so that at any given instance, different disks are accessing the video or multimedia data for different streams. Access to the disks for reading the continuous media files is scheduled periodically, with the period equal to the back time of the stripes. Because each disk read command retrieves data for a fixed play back time, if the first read command for a continuous media stream request can be scheduled to complete on a disk within a playback time, all subsequent read commands are also guaranteed to not interfere with read commands of other streams. Data is delivered directly from the disk array to the communication network by a stream controller without being sent to the host system. Disk storage is utilized efficiently by allocating disk space in units of cylinders and storing the variable size stripes of video in packed format.

Abstract translation: 一种用于将多媒体视频数据从服务器（主处理器）传送到连接到通信网络的多个客户端的方法和装置。 更具体地说，利用本发明，即使这样的单元导致可变长度的条带，预处理的视频和多媒体数据分组以固定的播放时间为单位在磁盘上条带化。 为了提供多个视频或连续媒体流，阵列中的磁盘被同时访问，使得在任何给定的实例中，不同的磁盘正在访问用于不同流的视频或多媒体数据。 周期性地定期访问用于读取连续媒体文件的磁盘，周期等于条带的后续时间。 由于每个磁盘读取命令检索固定播放时间的数据，如果连续媒体流请求的第一个读取命令可以在播放时间内调度到一个磁盘上完成，所有后续的读取命令也保证不会干扰读取 其他流的命令。 数据通过流控制器直接从磁盘阵列传送到通信网络，而不会发送到主机系统。 通过以圆柱体为单位分配磁盘空间并以压缩格式存储视频的可变大小条带来有效地利用磁盘存储。