公开(公告)号：US08110870B2

公开(公告)日：2012-02-07

申请号：US12502251

申请日：2009-07-14

申请人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Tetsu Kachi

发明人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Masakazu Kanechika ,  Tetsu Kachi

IPC分类号： H01L29/66

CPC分类号： H01L29/8122 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/1037 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/42316 ,  H01L29/7828 ,  H01L29/7832 ,  H01L29/7838 ,  H01L29/812

摘要： A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction.

摘要翻译： 半导体器件具有具有表面层和p型半导体区域的半导体衬底，其中表面层包括接触区域，沟道区域和漂移区域，沟道区域与接触区域相邻并与其接触， 漂移区域与沟道区域相邻并且与沟道区域接触并且至少部分地包括n型杂质，并且p型半导体区域与漂移区域和沟道的后表面的至少一部分接触 区域，设置在所述表面层上并电连接到所述接触区域的主电极，设置在所述表面层上并且从所述接触区域的一部分的上方延伸到所述漂移区域的至少一部分之上的栅电极， 以及至少覆盖所述接触区域的部分并且至少覆盖所述漂移区域的部分的绝缘层。 栅极电极和接触区域被绝缘层绝缘，栅电极和漂移区域直接接触形成肖特基结。

公开(公告)号：US08008749B2

公开(公告)日：2011-08-30

申请号：US11667735

申请日：2005-11-14

申请人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

发明人： Masahiro Sugimoto ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima ,  Tetsu Kachi

IPC分类号： H01L29/20

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/41 ,  H01L29/778 ,  H01L29/7788 ,  H01L29/8122

摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

摘要翻译： 半导体器件设置有漏电极22，半导体基板32，覆盖半导体基板32的一部分表面的电流调节层42，并在半导体基板的表面留下未被覆盖的表面55 板32，覆盖电流调节层42的表面的半导体层50和形成在半导体层50的表面的源电极62.漂移区56，沟道形成区54和源极区52是 形成在半导体层50内。漏电极22连接到电源的第一端子，源电极62连接到电源的第二端子。 利用该半导体层50，可以提高耐压或减少电流泄漏的发生。

公开(公告)号：US07800130B2

公开(公告)日：2010-09-21

申请号：US11795117

申请日：2006-01-20

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/778

CPC分类号： H01L29/452 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.

摘要翻译： 半导体器件10包括由p型氮化镓制成的下半导体层26和由n型AlGaN制成的上半导体层28之间的异质结，其中上半导体层28具有比下半导体层26更大的带隙 半导体器件10还包括形成在上半导体层28的顶表面的一部分上的漏极32，形成在上半导体层28的顶表面的不同部分上的源极34和栅电极 36电连接到下半导体层26.半导体器件10可以正常工作。

公开(公告)号：US20100117119A1

公开(公告)日：2010-05-13

申请号：US12595253

申请日：2008-04-07

申请人： Tsutomu Uesugi ,  Kenji Ito ,  Osamu Ishiguro ,  Tetsu Kachi ,  Masahiro Sugimoto

发明人： Tsutomu Uesugi ,  Kenji Ito ,  Osamu Ishiguro ,  Tetsu Kachi ,  Masahiro Sugimoto

IPC分类号： H01L29/778

CPC分类号： H01L29/2003 ,  H01L29/045 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7828

摘要： A semiconductor device 10 is provided with a first hetero junction 40b configured with two types of nitride semiconductors having different bandgap energy from each other, a second hetero junction 50b configured with two types of nitride semiconductors having different bandgap energy from each other, and a gate electrode 58 facing the second hetero junction 50b. The second hetero junction 50b is configured to be electrically connected to the first hetero junction 40b. The first hetero junction 40b is a c-plane and the second hetero junction 50b is either an a-plane or an m-plane.

摘要翻译： 半导体器件10设置有由彼此具有不同带隙能量的两种类型的氮化物半导体构成的第一异质结40b，由具有彼此具有不同带隙能量的两种类型的氮化物半导体构成的第二异质结50b，以及栅极 电极58面对第二异质结50b。 第二异质结50b被配置为电连接到第一异质结40b。 第一异质结40b是c面，第二异质结50b是a面或m面。

公开(公告)号：US20080073652A1

公开(公告)日：2008-03-27

申请号：US11632665

申请日：2005-06-22

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/205 ,  H01L21/338 ,  H01L29/778

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： The semiconductor device has a stacked structure in which a p-GaN layer 32, an SI-GaN layer 62, and an AlGaN layer 34 are stacked, and has a gate electrode 44 that is formed at a top surface side of the AlGaN layer 34. A band gap of the AlGaN layer 34 is wider than a band gap of the p-GaN layer 32 and the SI-GaN layer 62. Moreover, impurity concentration of the SI-GaN layer 62 is less than 1×1017 cm−3. The semiconductor devices comprising III-V semiconductors that have a stable normally-off operation are realized.

摘要翻译： 半导体器件具有层叠p-GaN层32，SI-GaN层62和AlGaN层34的堆叠结构，并且具有形成在AlGaN层34的顶面侧的栅电极44 AlGaN层34的带隙比p-GaN层32和SI-GaN层62的带隙宽。另外，SI-GaN层62的杂质浓度小于1×10 17 / SUP> cm 3 -3。 实现了具有稳定的常关断操作的包括III-V半导体的半导体器件。

公开(公告)号：US07211839B2

公开(公告)日：2007-05-01

申请号：US10771528

申请日：2004-02-05

申请人： Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi

发明人： Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi

IPC分类号： H01L29/793

CPC分类号： H01L29/7788 ,  H01L29/0646 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/7828

摘要： A semiconductor device is formed by a first layer 32 composed of AlGaN, a second layer 42 composed of GaN, a gate electrode 34, a source electrode 38, and a drain electrode 28. The first layer 32 has a region 32a formed between the gate electrode 34 and the second layer 42. A channel is formed in the vicinity of the boundary 24 of the first layer 32 and the second layer 42. The second layer 42 has p-type conductivity and is in contact with the source electrode 38. When electrons flow in the channel, the electrons collide with surrounding atoms, and holes are formed. If holes are accumulated inside the semiconductor device, the presence of the accumulated holes causes dielectric breakdown. In the semiconductor device of the invention, holes are discharged to the outside of the device thorough the second layer 42 and the source electrode 38, and accumulation of holes can be prevented.

摘要翻译： 半导体器件由由AlGaN构成的第一层32，由GaN构成的第二层42，栅电极34，源电极38和漏电极28形成。 第一层32具有形成在栅电极34和第二层42之间的区域32a。 在第一层32和第二层42的边界24附近形成沟道。 第二层42具有p型导电性并且与源电极38接触。当电子在沟道中流动时，电子与周围的原子碰撞，形成孔。 如果在半导体器件内部积聚有孔，则积聚的孔的存在引起介质击穿。 在本发明的半导体器件中，通过第二层42和源电极38将孔排放到器件的外部，并且可以防止空穴的累积。

公开(公告)号：US20050133799A1

公开(公告)日：2005-06-23

申请号：US11034261

申请日：2005-01-13

申请人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

发明人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

IPC分类号： H01L33/00 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01L33/60 ,  H01L21/00 ,  H01L27/10 ,  H01L27/15 ,  H01L29/26 ,  H01L29/74 ,  H01L31/12

CPC分类号： H01L33/46 ,  H01L33/0095 ,  H01L33/32

摘要： A process of forming separation grooves for separating a semiconductor wafer into individual light-emitting devices, a process for thinning the substrate, process for adhering the wafer to the adhesive sheet to expose a substrate surface on the reverse or backside of the wafer, a scribing process for forming split lines in the substrate for dividing the wafer into light-emitting devices, and a process of forming a mirror structure comprising a light transmission layer, a reflective layer, and a corrosion-resistant layer, which are laminated in sequence using sputtering or deposition processes. Because the light transmission layer is laminated on the adhesive sheet, gases normally volatilized from the adhesion materials are sealed and do not chemically combine with the metal being deposited as the reflective layer. As a result, reflectivity of the reflective layer can be maintained.

公开(公告)号：US07897987B2

公开(公告)日：2011-03-01

申请号：US12382040

申请日：2009-03-06

申请人： Mitsuhiro Inoue ,  Kenji Ito ,  Kazuyohi Tomita ,  Tetsu Kachi ,  Takahiro Kozawa ,  Satoru Kato ,  Tadashi Ichikawa

发明人： Mitsuhiro Inoue ,  Kenji Ito ,  Kazuyohi Tomita ,  Tetsu Kachi ,  Takahiro Kozawa ,  Satoru Kato ,  Tadashi Ichikawa

IPC分类号： H01L33/00

CPC分类号： H01L33/504 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A light-emitting device includes a light-emitting diode, a red light-emitting phosphor layer, a yellow light-emitting phosphor layer, and a blue light-emitting phosphor layer. These layers are stacked in the stacking sequence of the yellow, blue, and red phosphor layers in order of increasing distance from the LED. The stacking sequence of the yellow and blue phosphor layers is first determined in such a manner that these layers do not interact with each other. The stacking sequence of the red and yellow phosphor layers and the stacking sequence of the red and blue phosphor layers are determined by the discriminant D. This determination of the stacking sequence suppresses a reduction in the conversion efficiency of the phosphors due to concentration quenching, improving the emission efficiency of the light-emitting device.

摘要翻译： 发光装置包括发光二极管，红色发光荧光体层，黄色发光荧光体层和蓝色发光荧光体层。 这些层按照与LED的距离增加的顺序堆叠在黄色，蓝色和红色荧光体层的堆叠顺序中。 首先以这样的方式确定黄色和蓝色磷光体层的堆叠顺序，使得这些层彼此不相互作用。 红色和黄色荧光体层的堆叠顺序和红色和蓝色荧光体层的堆叠序列由判别式D确定。堆积顺序的确定抑制了由于浓度淬灭引起的荧光体的转换效率的降低，改进 发光装置的发光效率。

公开(公告)号：US07342364B2

公开(公告)日：2008-03-11

申请号：US11226373

申请日：2005-09-15

申请人： Satoru Kato ,  Tetsu Kachi ,  Kazuyoshi Tomita ,  Hiroshi Ito ,  Masanori Kojima

发明人： Satoru Kato ,  Tetsu Kachi ,  Kazuyoshi Tomita ,  Hiroshi Ito ,  Masanori Kojima

IPC分类号： H05B37/00

CPC分类号： H05B33/0845 ,  B82Y20/00 ,  H01S5/34333 ,  H05B33/0818 ,  Y02B20/346

摘要： A light source comprising a light emitting diode comprising a GaN-based compound and having a single quantum well structure, and a driving voltage source for applying a pulse voltage to the light emitting diode, wherein a voltage at a low level of the pulse voltage is set to a voltage lower than a voltage at which a fall time of the light emitting diode is made the longest.

摘要翻译： 一种光源，包括包含GaN基化合物并且具有单量子阱结构的发光二极管，以及用于向所述发光二极管施加脉冲电压的驱动电压源，其中所述脉冲电压为低电平的电压为 设定为低于发光二极管的下降时间最长的电压的电压。

公开(公告)号：US06960485B2

公开(公告)日：2005-11-01

申请号：US10375135

申请日：2003-02-28

申请人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

发明人： Toshiya Uemura ,  Naohisa Nagasaka ,  Masaki Hashimura ,  Atsuo Hirano ,  Hiroshi Tadano ,  Tetsu Kachi ,  Hideki Hosokawa

IPC分类号： H01L33/00 ,  H01L33/10 ,  H01L33/32 ,  H01L33/46 ,  H01L33/60 ,  H01L21/00

CPC分类号： H01L33/46 ,  H01L33/0095 ,  H01L33/32

摘要： A process of forming separation grooves for separating a semiconductor wafer into individual light-emitting devices, a process for thinning the substrate, process for adhering the wafer to the adhesive sheet to expose a substrate surface on the reverse or backside of the wafer, a scribing process for forming split lines in the substrate for dividing the wafer into light-emitting devices, and a process of forming a mirror structure comprising a light transmission layer, a reflective layer, and a corrosion-resistant layer, which are laminated in sequence using sputtering or deposition processes. Because the light transmission layer is laminated on the adhesive sheet, gases normally volatilized from the adhesion materials are sealed and do not chemically combine with the metal being deposited as the reflective layer. As a result, reflectivity of the reflective layer can be maintained.

摘要翻译： 形成用于将半导体晶片分离成各个发光器件的分离槽的工艺，用于使基板变薄的工艺，将晶片粘附到粘合片上以暴露晶片背面或背面的基板表面的处理，划线 在基板上形成分割线以将晶片分割成发光器件的工艺，以及形成包括透光层，反射层和耐腐蚀层的反射镜结构的工艺，其顺序地使用溅射 或沉积工艺。 由于透光层层压在粘合片上，所以通常从粘合材料挥发的气体被密封，并且不与作为反射层沉积的金属化学结合。 结果，可以保持反射层的反射率。