公开(公告)号：US20190109080A1

公开(公告)日：2019-04-11

申请号：US16200843

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4825 ,  H01L21/76879 ,  H01L21/7688 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/10126 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/35121 ,  H01L2924/013 ,  H01L2924/00014

Abstract: An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of the substrate, and a dielectric material adjacent and in contact with the edge wall and an adjacent portion of the surface of the substrate. The dielectric material has a profile tapering downward from adjacent the edge wall toward the substrate. Other electronic devices include a substrate and a solder mask over the substrate. The solder mask defines an opening therethrough. A supplemental mask is within the opening of the solder mask, and has a sidewall that slopes away from the solder mask. A conductive structure is adjacent and in contact with at least one of the solder mask or the supplemental mask.

公开(公告)号：US09741612B2

公开(公告)日：2017-08-22

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L23/544 ,  H01L21/683 ,  H01L23/48 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US20250079376A1

公开(公告)日：2025-03-06

申请号：US18951177

申请日：2024-11-18

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  David R. Hembree

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.

公开(公告)号：US20240429172A1

公开(公告)日：2024-12-26

申请号：US18827526

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Ruei Ying Sheng ,  Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.

公开(公告)号：US12148727B2

公开(公告)日：2024-11-19

申请号：US17174905

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  David R. Hembree

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.

公开(公告)号：US20240139940A1

公开(公告)日：2024-05-02

申请号：US18409692

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： Kuan Wei Tseng ,  Brandon P. Wirz

IPC: B25J9/16 ,  B25J13/08 ,  B25J19/02 ,  H01L21/67 ,  H01L23/00 ,  H05K13/08

CPC classification number: B25J9/1633 ,  B25J13/085 ,  B25J19/028 ,  H01L21/67144 ,  H01L24/75 ,  H05K13/082 ,  H01L2224/7565 ,  H01L2224/7592

Abstract: An apparatus for handling microelectronic devices comprises a pick arm having a pick surface configured for receiving a microelectronic device thereon, drives for moving the pick arm and reorienting the pick surface in the X, Y and Z planes and about a horizontal rotational axis and a vertical rotational axis, and a sensor device carried by the pick arm and configured to detect at least one of at least one magnitude of force and at least one location of force applied between the pick surface and a structure contacted by the pick surface or a structure and a microelectronic device carried on the pick surface.

公开(公告)号：US11955345B2

公开(公告)日：2024-04-09

申请号：US17315588

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Liang Chun Chen

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/56 ,  H01L21/4875 ,  H01L21/4878

Abstract: Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.

公开(公告)号：US20240038707A1

公开(公告)日：2024-02-01

申请号：US17875778

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Cassie M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/13019 ,  H01L2224/13582 ,  H01L2224/81815 ,  H01L2224/13147 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13124 ,  H01L2224/13184 ,  H01L2224/13157 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/1369 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13613 ,  H01L2224/13609 ,  H01L2224/13618 ,  H01L2224/1362

Abstract: In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

公开(公告)号：US20240006223A1

公开(公告)日：2024-01-04

申请号：US18368449

申请日：2023-09-14

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/6836 ,  H01L21/4814 ,  H01L23/481

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

公开(公告)号：US11784050B2

公开(公告)日：2023-10-10

申请号：US17241386

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L21/76859 ,  H01L21/78 ,  H01L21/26513

Abstract: A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.