公开(公告)号：US20240332002A1

公开(公告)日：2024-10-03

申请号：US18743882

申请日：2024-06-14

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Farrell M. Good

IPC: H01L21/02 ,  C01B32/00 ,  C01B33/00 ,  C23C16/04 ,  C23C16/452

CPC classification number: H01L21/02167 ,  C01B32/00 ,  C01B33/00 ,  C23C16/045 ,  C23C16/452 ,  H01L21/02274 ,  H01L21/02381 ,  H01L2221/1047

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US20240215268A1

公开(公告)日：2024-06-27

申请号：US18391122

申请日：2023-12-20

Applicant: Micron Technology, Inc.

Inventor： Zhao Zhao ,  Trevor J. Plaisted ,  Stephen W. Russell ,  Farrell M. Good ,  Sangeetha P. Komanduri ,  Sandra L. Tagg ,  Nathan A. Wilkerson

IPC: H10B63/00 ,  H10B63/10

CPC classification number: H10B63/845 ,  H10B63/10

Abstract: Methods, systems, and devices for a single plug flow for a memory device are described. In some examples, the memory device may include one or more plugs formed above respective bit line plates. The plugs may include a liner and one or more sacrificial materials that are removed during a subsequent etching operation. Accordingly, pillars may be formed above the plugs, and may be generally aligned with the respective bit line plates.

公开(公告)号：US20230387229A1

公开(公告)日：2023-11-30

申请号：US17804530

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Everett A. McTeer ,  Farrell M. Good ,  John M. Meldrim ,  Jordan D. Greenlee ,  Justin D. Shepherdson ,  Naiming Liu ,  Yifen Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L29/4234 ,  H01L29/40117 ,  H01L27/11582

Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20220376176A1

公开(公告)日：2022-11-24

申请号：US17818313

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US11444243B2

公开(公告)日：2022-09-13

申请号：US16665679

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Santanu Sarkar ,  Robert K. Grubbs ,  Farrell M. Good ,  Adam W. Saxler ,  Andrea Gotti

IPC: H01L45/00

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

公开(公告)号：US20220238324A1

公开(公告)日：2022-07-28

申请号：US17248376

申请日：2021-01-22

Applicant: Micron Technology, Inc.

Inventor： Farrell M. Good ,  Robert K. Grubbs

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/448 ,  C23C16/50 ,  C23C16/34

Abstract: A method of forming a microelectronic device comprises treating a base structure with a first precursor to adsorb the first precursor to a surface of the base structure and form a first material. The first precursor comprises a hydrazine-based compound including Si—N—Si bonds. The first material is treated with a second precursor to covert the first material into a second material. The second precursor comprises a Si-centered radical. The second material is treaded with a third precursor to covert the second material into a third material comprising Si and N. The third precursor comprises an N-centered radical. An ALD system and a method of forming a seal material through ALD are also described.

公开(公告)号：US20200274060A1

公开(公告)日：2020-08-27

申请号：US16870137

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US10249819B2

公开(公告)日：2019-04-02

申请号：US14244486

申请日：2014-04-03

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US20180123036A1

公开(公告)日：2018-05-03

申请号：US15857873

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Campbell ,  Irina Vasilyeva ,  Farrell M. Good ,  Vishwanath Bhat ,  Kyuchul Chong

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1675

Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.

公开(公告)号：US20240268240A1

公开(公告)日：2024-08-08

申请号：US18634079

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Farrell M. Good ,  Robert K. Grubbs ,  Gurpreet S. Lugani

IPC: H10N70/00

CPC classification number: H10N70/063 ,  H10N70/826 ,  H10N70/882

Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.