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    Memory Circuitry And Method Used In Forming Memory Circuitry
    12.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240029794A1

    公开(公告)日：2024-01-25

    申请号：US17868118

    申请日：2022-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Lifang Xu ,  Anna Maria Conti ,  Harsh Narendrakumar Jain ,  H. Montgomery Manning

    IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

    CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. The developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. A second layer of imageable resist is formed directly above the two opposing flights of stairs. The second layer is exposed to actinic radiation and developed to form a second opening there-through. The second opening exposes all of the stairs of one of the two opposing flights. The second layer is directly above all of the stairs in the other of the two opposing flights. The developed second layer is used in a plurality of alternating etching and lateral-trimming steps that widens the second opening, lengthens at least one of the two opposing flights of stairs, and extends the two opposing flights of stairs deeper into the stack. Other embodiments, including structure, are disclosed.

    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    17.
    发明申请
    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20210125920A1

    公开(公告)日：2021-04-29

    申请号：US16664618

    申请日：2019-10-25

    Applicant: Micron Technology, Inc.

    Inventor： Yi Hu ,  Harsh Narendrakumar Jain ,  Matthew J. King

    IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

    STAIRCASE LANDING PADS VIA RIVETS
    19.
    发明公开
    STAIRCASE LANDING PADS VIA RIVETS 审中-公开

    公开(公告)号：US20240258233A1

    公开(公告)日：2024-08-01

    申请号：US18420538

    申请日：2024-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Yiping Wang ,  Harsh Narendrakumar Jain

    IPC: H01L23/528 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/76877 ,  H01L29/4011

    Abstract: Methods, systems, and devices for staircase landing pads via rivets are described. A memory device may include a staircase region with a stack of materials that includes a set of word lines, where the set of word lines progressively decrease in length to form a staircase structure. The staircase region may additionally include a rivet that couples a first word line from the set of word lines with a conductive pillar. Additionally, the conductive pillar may traverse the stack perpendicularly to the set of word lines and may couple the first word line with supporting circuitry. In some cases, a first thickness of the first word line adjacent to the conductive pillar may be greater than a second thickness of other word lines adjacent to the conductive pillar. The staircase region may additionally include an oxide material that isolates the conductive pillar from the other word lines.

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