中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.019 seconds)

    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
    11.
    发明申请
    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS 有权

    公开(公告)号：US20230039026A1

    公开(公告)日：2023-02-09

    申请号：US17396825

    申请日：2021-08-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

    FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS
    12.
    发明申请
    FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS 有权

    公开(公告)号：US20230034752A1

    公开(公告)日：2023-02-02

    申请号：US17833466

    申请日：2022-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki

    IPC: G11C16/16 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

    Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.

    ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A MEMORY SUB-SYSTEM
    14.
    发明申请
    ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220310165A1

    公开(公告)日：2022-09-29

    申请号：US17669074

    申请日：2022-02-10

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Lawrence Celso Miranda

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04

    Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and applies, during a first time period of the program operation, a ramping wordline voltage to a set of wordlines associated with the memory array. The control logic causes, during the first time period, a disconnection of a set of pillars associated with the set of memory cells from a voltage supply and ground voltage, wherein each pillar corresponds to a programming level of a set of programming levels. The control logic further causes, during a second time period of the program operation, a set of programming pulses to be applied to the set of memory cells, wherein each programming pulse of the set of programming pulses programs each programming level of the set of programming levels associated with the identified set of memory cells.

    VECTOR ELEMENT MULTIPLICATION IN NAND MEMORY
    15.
    发明申请
    VECTOR ELEMENT MULTIPLICATION IN NAND MEMORY 有权

    公开(公告)号：US20250124102A1

    公开(公告)日：2025-04-17

    申请号：US18757909

    申请日：2024-06-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dmitri Yudanov ,  Lawrence Celso Miranda ,  Sheyang Ning ,  Aliasger Zaidy

    IPC: G06F17/16

    Abstract: Memories might include a plurality of strings of series-connected memory cells, each corresponding to a respective digit of a plurality of digits of a multiplicand, and might further include a controller configured to cause the memory to generate respective current flows through the plurality of strings of series-connected memory cells for each digit of a plurality of digits of a multiplier having respective current levels indicative of values of each digit of the plurality of digits of the multiplier times the multiplicand, to convert the respective current levels to respective digital values indicative of the values and magnitudes of each digit of the plurality of digits of the multiplier times the multiplicand, and to sum the respective digital value of each digit of the plurality of digits of the multiplier.

    MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
    17.
    发明公开
    MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20230397401A1

    公开(公告)日：2023-12-07

    申请号：US17830145

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Song Guo ,  Yuan He

    IPC: H01L27/108 ,  G11C5/02

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  G11C5/02

    Abstract: Methods, systems, and devices for memory cell capacitor structures for three-dimensional memory arrays are described. A memory device may include a memory array including multiple levels of memory cells that are each separated from another level by a respective dielectric layer. A memory cell at a first level of the memory array may include a channel portion and a capacitor operable to store a logic state of the memory cell. A first portion of the capacitor may be located between the channel portion and a voltage source coupled with the memory cell. A second portion of the capacitor may be in a cavity in a dielectric layer between the first level and a second level of the memory array. The second portion of the capacitor may be located between the channel portion and a word line coupled with a channel portion of a second memory cell at the second level.

    APPARATUS AND METHODS FOR DETERMINING MEMORY CELL DATA STATES
    18.
    发明公开
    APPARATUS AND METHODS FOR DETERMINING MEMORY CELL DATA STATES 审中-公开

    公开(公告)号：US20230274786A1

    公开(公告)日：2023-08-31

    申请号：US17681976

    申请日：2022-02-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Ting Luo ,  Luyen Vu

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C7/10

    CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/12005 ,  G11C7/1069 ,  G11C7/1096

    Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

    Managing dielectric stress of a memory device using controlled ramping slopes
    20.
    发明授权
    Managing dielectric stress of a memory device using controlled ramping slopes 有权

    公开(公告)号：US11494084B2

    公开(公告)日：2022-11-08

    申请号：US17119576

    申请日：2020-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Sheyang Ning ,  Lawrence Miranda

    IPC: G06F3/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/04

    Abstract: Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.

Patent Agency Ranking