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    Techniques for forming self-aligned memory structures
    12.
    发明授权
    Techniques for forming self-aligned memory structures 有权

    公开(公告)号：US12219883B2

    公开(公告)日：2025-02-04

    申请号：US17881274

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

    Access line grain modulation in a memory device
    13.
    发明授权
    Access line grain modulation in a memory device 有权

    公开(公告)号：US12087358B2

    公开(公告)日：2024-09-10

    申请号：US17236700

    申请日：2021-04-21

    Applicant: Micron Technology, Inc.

    Inventor： David Ross Economy ,  Stephen W. Russell

    IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

    CPC classification number: G11C13/003 ,  H10B63/84 ,  H10N70/021 ,  H10N70/801

    Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

    Word line structures for three-dimensional memory arrays
    17.
    发明授权
    Word line structures for three-dimensional memory arrays 有权

    公开(公告)号：US11804252B2

    公开(公告)日：2023-10-31

    申请号：US17656283

    申请日：2022-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Lorenzo Fratin ,  Enrico Varesi ,  Paolo Fantini

    IPC: G11C8/00 ,  G11C8/10 ,  G11C8/14 ,  H01L23/522 ,  H10B63/00 ,  H10N70/00

    CPC classification number: G11C8/10 ,  G11C8/14 ,  H01L23/5226 ,  H10B63/84 ,  H10N70/021 ,  H10N70/826

    Abstract: Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.

    Cross-point memory array and related fabrication techniques
    18.
    发明授权
    Cross-point memory array and related fabrication techniques 有权

    公开(公告)号：US10950663B2

    公开(公告)日：2021-03-16

    申请号：US15961547

    申请日：2018-04-24

    Applicant: Micron Technology, inc.

    Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

    IPC: H01L27/24 ,  H01L27/11514 ,  H01L45/00

    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

    TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES
    19.
    发明申请
    TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES 有权

    公开(公告)号：US20210050521A1

    公开(公告)日：2021-02-18

    申请号：US16539932

    申请日：2019-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

    CROSS-POINT MEMORY ARRAY AND RELATED FABRICATION TECHNIQUES
    20.
    发明申请
    CROSS-POINT MEMORY ARRAY AND RELATED FABRICATION TECHNIQUES 审中-公开

    公开(公告)号：US20190326357A1

    公开(公告)日：2019-10-24

    申请号：US15961547

    申请日：2018-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

    IPC: H01L27/24 ,  H01L27/11514

    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

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